Vertical FET Self-Aligned Top Source Drain Junction
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Solution Overview
Problem
Forming a good junction overlap of the top source and drain terminal to the gate in vertical field-effect transistors (VFETs) is difficult due to thinning of the high-k gate dielectric, leading to reliability issues and degraded transistor performance.
Innovation Solution
A method involving the formation of epitaxial regions with different doping concentrations and thicknesses, along with a self-aligned recrystallization process, to accurately define the top source and drain junction, ensuring lateral overlap of the gate without thinning the high-k gate dielectric.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional top source and drain junction definition is performed during late metal gate recess and reactive ion etching of top spacers, then the process is simpler, but good junction overlap of the top source and drain terminal to the gate becomes difficult due to thinning of the high-k gate dielectric
Solution Approach 1:
The top source and drain junctions are formed preliminarily through selective epitaxial growth before the gate dielectric thinning process. The epitaxial regions are grown on exposed semiconductor surfaces at specific locations, establishing precise junction positions in advance. This preliminary formation ensures that when subsequent gate dielectric thinning and spacer removal occur, the junction overlap is already properly established and cannot be degraded by later process variations.
2Manufacturing precision
If the high-k gate dielectric is thinned to achieve better junction overlap, then the overlap improves, but reliability issues occur
Solution Approach 1:
Instead of achieving junction overlap by thinning the gate dielectric (conventional approach), the invention inverts the sequence: junctions are formed first through selective epitaxial growth on exposed surfaces, then the gate dielectric is thinned. This reversal ensures that junction precision is established before any dielectric degradation occurs, eliminating the trade-off between overlap and reliability.
3Manufacturing precision
If selective epitaxial growth is used to form top source and drain regions, then self-aligned junctions with proper overlap are achieved, but the process complexity increases
Solution Approach 1:
The selective epitaxial growth process is self-aligned by nature: epitaxial regions grow only on exposed semiconductor surfaces where mask patterns have been removed, automatically positioning junctions with precise alignment to the gate structure. The process uses the existing mask pattern and exposed surface geometry to self-determine junction locations, eliminating the need for additional alignment steps or complex positioning mechanisms.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach guarantees a self-aligned top junction with improved transistor performance by ensuring sufficient lateral overlap of the gate, reducing external resistance and enhancing overall device reliability.
Implementation Method 1
recrystallizing portions of the amorphous semiconductor layer in contact with the top surface of the channel fin to form recrystallized regions
Implementation Method 2
forming a first epitaxial region above the channel fin and a second epitaxial region above the first epitaxial region
Data Source
AI summary
A vertical field effect transistor includes a first epitaxial region in contact with a top surface of a channel fin extending vertically from a bottom source/drain located above a substrate, a second epitaxial region above the first epitaxial region having a horizontal thickness that is larger than a horizontal thickness of the first epitaxial region. The first epitaxial region and the second epitaxial region form a top source/drain region of the semiconductor structure. The first epitaxial region has a first doping concentration and the second epitaxial region has a second doping concentration that is lower than the first doping concentration. A top spacer, adjacent to the first epitaxial region and the second epitaxial region, is in contact with a top surface of a high-k metal gate stack located around the channel fin and in contact with a top surface of a first dielectric layer disposed between adjacent channel fins.