Vertical FET Top Source Drain Trench Confinement
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Solution Overview
Problem
Vertical field effect transistors (FETs) face challenges in optimizing the top source/drain region, which requires low resistance and a large contact landing pad while avoiding shorting to the gate and bottom source/drain contacts.
Innovation Solution
The method involves forming vertical fins on a substrate with gate material and encapsulation on the sides, creating a trench that exposes the top fins, and forming a top source/drain as an epitaxial layer with a wide perpendicular and narrow parallel configuration to the fins, using epitaxial growth within the confinement trench to avoid shorting.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the top source/drain region is made larger to provide a large contact landing pad, then the contact area is improved, but the risk of shorting to the gate or bottom source/drain contacts increases
Solution Approach 1:
The top source/drain region is formed with an asymmetric footprint that extends primarily in the first lateral direction (perpendicular to fins) while being constrained in the second lateral direction (parallel to fins). This dimensional differentiation allows the contact area to be enlarged without proportionally increasing the risk of shorting, as the extension is directed along the dimension where shorting risk is lower.
Solution Approach 2:
The top source/drain region exhibits different dimensional characteristics in different lateral directions: it has a larger extent in the first lateral direction (perpendicular to fins) compared to its extent in the second lateral direction (parallel to fins). This local quality differentiation optimizes the contact area while maintaining adequate spacing from gate and bottom source/drain contacts in the critical direction.
2Reliability
If the top source/drain region is made larger to reduce resistance, then the electrical conductivity is improved, but the device complexity increases due to additional confinement structures
Solution Approach 1:
The trench structure is formed prior to the formation of the top source/drain region, establishing the lateral confinement boundaries in advance. This preliminary action defines the geometry of the top source/drain region, allowing it to be formed with the desired low-resistance characteristics while automatically maintaining the appropriate spacing from gate and bottom source/drain contacts, thereby reducing the need for additional complex confinement structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration provides low resistance, a large contact landing pad, and reduces the risk of shorting to the gate or bottom source/drain contacts, enhancing the performance of integrated circuits and computer processors.
Implementation Method 1
forming a top source or drain on top of the one or more fins such that the top source or drain is laterally confined by the trench
Data Source
AI summary
Techniques relate to forming a vertical field effect transistor (FET). One or more fins are formed on a bottom source or drain of a substrate, and one or more fins extend in a vertical direction. Gate material is formed to be positioned on sides of the one or more fins. Gate encapsulation material is formed on sides of the gate material to form a trench, such that top portions of the one or more fins are exposed in the trench. A top source or drain is formed on top of the one or more fins such that the top source or drain is laterally confined by the trench in a lateral direction that is parallel to the one or more fins.