Vertical FET with Trench Gate and Source Drain Structures
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Solution Overview
Problem
Conventional CMOS technologies for switches in cellular devices are expensive and occupy valuable chip real estate due to their manufacturing costs and large footprint, limiting device density.
Innovation Solution
A vertical field effect transistor (FET) structure is developed with vertically oriented gate and source/drain trenches, using a solid source dopant and silicide on the source/drain regions, allowing for higher device density by forming FETs in separate trenches with a semiconductor body between them.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional CMOS technologies are used for switches, then the manufacturing process is well-established and reliable, but the device occupies large chip area and has high manufacturing cost
Solution Approach 1:
The patent transitions from planar 2D FET structures to vertical 3D FET structures by forming gate trenches and source/drain trenches perpendicular to the substrate surface. This dimensional change allows multiple FETs to be stacked vertically, significantly increasing device density while maintaining manufacturing reliability through adapted conventional processes.
Solution Approach 2:
The patent divides the FET structure into separate vertical trenches: gate trenches for the gate structure and source/drain trenches for the source and drain regions. This segmentation allows independent formation and optimization of each component while enabling higher packing density on the chip.
2Ease of manufacture
If conventional planar FET structures are used, then the manufacturing process is simpler, but the device density on chip is low
Solution Approach 1:
The invention achieves higher device density by forming vertical gate structures and source/drain regions that extend into the substrate thickness direction. This vertical configuration allows multiple device layers to be stacked, increasing productivity without substantially complicating the manufacturing process as it builds upon conventional trench formation and doping techniques.
3Productivity
If vertical FET structure with separate trenches is used, then device density is significantly increased, but manufacturing process complexity increases
Solution Approach 1:
The patent segments the vertical FET into distinct gate trenches and source/drain trenches that can be formed separately using standard photolithography and etching processes. This segmentation maintains manufacturing feasibility while achieving high device density through vertical stacking of segmented components.
Solution Approach 2:
By transitioning to vertical trenches extending into the substrate, the patent increases device density in the third dimension without requiring proportionally more complex manufacturing equipment, as the processes are adaptations of conventional planar techniques rather than entirely new methods.
4Ease of manufacture
If conventional FET structures are used, then manufacturing cost is high, but the structure is well-understood and manufacturable
Solution Approach 1:
The vertical FET structure utilizes the substrate thickness dimension to increase device density, which reduces the number of chips needed per wafer and lowers overall manufacturing cost per device. The structure remains manufacturable using adapted conventional processes for trench formation, doping, and silicide deposition.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The vertical FET structure significantly increases device density compared to conventional structures, enabling more efficient use of chip space and reducing manufacturing costs.
Implementation Method 1
a gate dielectric material lining the at least one vertically oriented gate trench
Implementation Method 2
vertically oriented source/drain regions extending into the substrate material and composed of conductive dopant material
Implementation Method 3
a silicide on the source/drain regions
Data Source
AI summary
The present disclosure relates to semiconductor structures and, more particularly, to vertical field effect transistors (FETS) and methods of manufacture. The structure includes: a substrate material; at least one vertically oriented gate structure extending into the substrate material and composed of a gate dielectric material and conductive gate material; and vertically oriented source/drain regions extending into the substrate material and composed of conductive dopant material and a silicide on the source/drain regions.