Vertical-Transport FET Trench Interconnects for Circuit Density
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Solution Overview
Problem
Improved structures and fabrication methods are needed for vertical-transport field-effect transistors to enhance their performance and efficiency.
Innovation Solution
A vertical-transport field-effect transistor structure is developed, featuring a source/drain region, a fin projecting from the source/drain region, a gate electrode on the semiconductor layer, and an interconnect located in a trench within the semiconductor layer, which is coupled with the source/drain region or gate electrode, allowing for increased circuit density and interconnectivity between non-adjacent transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional planar transistor structures are used, then fabrication is simpler, but circuit density is lower
Solution Approach 1:
The patent transitions from planar (2D) transistor structures to vertical (3D) transistor structures by orienting the channel perpendicular to the substrate surface. This dimensional change allows multiple transistors to be stacked vertically, significantly increasing circuit density without increasing the lateral footprint of the device.
2Productivity
If vertical-transport field-effect transistors are used, then circuit density is increased, but interconnection becomes more difficult
Solution Approach 1:
The patent introduces trench interconnects that extend vertically into the semiconductor layer, allowing electrical connections to be made at different vertical levels. This 3D interconnection approach enables routing signals between non-adjacent transistors without interfering with other wiring, solving the interconnection difficulty associated with vertical transistor structures.
3Adaptability or versatility
If trench interconnects are introduced, then interconnectivity between non-adjacent transistors is enabled, but fabrication complexity increases
Solution Approach 1:
The patent segments the interconnection system into multiple independent trench interconnects that can be formed at different locations and depths within the semiconductor layer. This segmentation allows flexible routing between non-adjacent transistors while maintaining modular fabrication processes, reducing overall fabrication complexity despite the added interconnectivity capability.
Data Source
AI summary
Structures and fabrication methods for vertical-transport field-effect transistors. The structure includes a vertical-transport field-effect transistor having a source/drain region located in a semiconductor layer, a fin projecting from the source/drain region in the semiconductor layer, and a gate electrode on the semiconductor layer and coupled with the fin. The structure further includes an interconnect located in a trench defined in the semiconductor layer. The interconnect is coupled with the source/drain region or the gate electrode of the vertical-transport field-effect transistor, and may be used to couple the source/drain region or the gate electrode of the vertical-transport field-effect transistor with a source/drain region or a gate electrode of another vertical-transport field-effect transistor.