Vertical Transport FET With Zero-Thickness Work Function Metal Variation
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Solution Overview
Problem
Current semiconductor fabrication methods for vertical transport FETs with multiple threshold voltages require complex processes involving WFM patterning and deposition, leading to accuracy issues and gate stack damage, and result in effective channel length variations due to different WFM thicknesses.
Innovation Solution
The method involves forming fins with varying germanium concentrations and depositing a germanium oxide layer on these fins, which is then annealed to increase germanium concentration, allowing for multiple threshold voltages without the need for WFM patterning, using a common gate stack across all devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If WFM patterning and deposition are used to achieve multiple threshold voltages, then different threshold voltages can be obtained, but process complexity increases and gate stack damage occurs
Solution Approach 1:
The patent applies local quality by varying the germanium concentration in specific regions of the channel to achieve different threshold voltages. Instead of using different WFM thicknesses across different devices, the invention modifies the local composition of the channel material (SiGe with varying Ge concentrations) to tune the threshold voltage while maintaining a uniform gate stack structure.
Solution Approach 2:
The invention changes the physical-chemical parameter of the channel material by controlling the germanium concentration in SiGe. By adjusting the Ge concentration parameter in the channel, the threshold voltage is tuned without requiring changes to the gate stack structure or WFM thickness, thereby simplifying the fabrication process.
2Adaptability or versatility
If different WFM thicknesses are used for multiple threshold voltages, then threshold voltage control is achieved, but effective channel length variations occur
Solution Approach 1:
The patent maintains uniform WFM thickness across all devices and instead varies the local germanium concentration in the channel material to achieve different threshold voltages. This approach ensures that the effective channel length remains consistent across all devices while still providing threshold voltage control through compositional variation.
Solution Approach 2:
The invention shifts from changing the WFM thickness parameter to changing the germanium concentration parameter in the channel. This parameter substitution eliminates the effective channel length variation problem while maintaining the ability to control threshold voltage through material composition adjustment.
3Adaptability or versatility
If WFM patterning is performed for multiple threshold voltages, then device differentiation is achieved, but gate stack damage occurs
Solution Approach 1:
The patent performs preliminary action by forming the complete gate stack uniformly across all devices first, and then differentiating the devices by varying the germanium concentration in the channel material. This reverse sequence avoids the need for subsequent WFM patterning that would damage the gate stack, as the differentiation is achieved through a non-invasive compositional modification.
Solution Approach 2:
The invention achieves device differentiation through local quality variation in the channel material (germanium concentration) rather than through WFM patterning. This approach differentiates devices without requiring any post-gate-stack processing, thereby preserving gate stack integrity while still achieving the desired device differentiation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the fabrication process by eliminating WFM patterning and achieving zero-thickness variation of the work function metal, while allowing for different threshold voltages in vertical FETs through controlled germanium concentration, thereby reducing process complexity and maintaining consistent gate stacks.
Implementation Method 1
depositing a germanium oxide layer on these fins, which is then annealed to increase germanium concentration
Data Source
AI summary
A technique relates to a semiconductor device. Fins are formed of varying concentrations of germanium. Gate material is formed on the fins. Source or drain (S/D) regions are adjacent to the fins, and transistor devices include the fins.