Vertical Fin Channel Structure for Dense, Reliable MOSFET Scaling
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Solution Overview
Problem
The scaling down of metal-oxide-semiconductor field-effect transistors (MOS-FETs) in semiconductor devices leads to deterioration in operational properties, necessitating improvements in integration density and reliability.
Innovation Solution
A semiconductor device design incorporating fin patterns, channel supporting patterns, channel patterns, gate electrodes, and isolation wall patterns, utilizing two-dimensional transition metal chalcogenides and transition metal oxides, with specific configurations to enhance integration and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If MOS-FETs are scaled down to increase integration density, then integration density is improved, but operational properties deteriorate
Solution Approach 1:
The patent introduces a vertical FinFET structure that extends the channel into the third dimension, allowing increased integration density in the planar direction while maintaining adequate channel length and control in the vertical direction. The fin structure provides topological isolation and improved gate control without requiring further lateral scaling.
Solution Approach 2:
The patent implements nested channel structures where first and second channels are positioned at different vertical levels (first channel supporting pattern at bottom surface, second channel supporting pattern at top surface), allowing multiple functional channels to be nested within a single footprint area, thereby increasing integration density while maintaining operational integrity.
2Quantity of substance
If channel patterns are extended vertically to improve integration density, then integration density is improved, but manufacturing precision becomes more difficult
Solution Approach 1:
The patent divides the channel structure into discrete segments - first channel supporting pattern at the bottom surface and second channel supporting pattern at the top surface, with isolation wall patterns separating adjacent channels. This segmentation allows each component to be formed and controlled independently, simplifying the manufacturing process while achieving vertical integration.
Solution Approach 2:
The patent introduces isolation wall patterns as intermediary structures that separate and define the boundaries between adjacent first and second channels. These isolation walls act as mediators that facilitate precise channel formation by providing physical and chemical barriers during manufacturing, enabling better control over channel dimensions and positioning.
3Quantity of substance
If fin patterns are used to create vertical channels, then integration density is improved, but device complexity increases
Solution Approach 1:
The fin pattern serves multiple functions simultaneously: it provides the vertical structure for channel formation, acts as a template for positioning channel supporting patterns, and creates topological isolation between adjacent devices. This multi-functionality reduces the need for additional separate components, thereby increasing integration density without proportionally increasing device complexity.
Data Source
AI summary
A semiconductor device may include a substrate including an active pattern, a fin pattern on the active pattern, a first channel supporting pattern on a bottom surface of the fin pattern and a second channel supporting pattern on a top surface of the fin pattern, a channel pattern on each of the first and second channel supporting patterns, a gate electrode on the channel pattern, a channel seed pattern provided on a side portion of the channel pattern, and an isolation wall pattern on a side surface of the channel seed pattern and a side surface of the fin pattern. The channel pattern may extend from a region on the first channel supporting pattern to a region on the second channel supporting pattern via a side surface of the fin pattern.