Co-fabricating Vertical FinFETs and Diodes via Dummy Gate Oxidation
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Solution Overview
Problem
Current technologies face challenges in co-fabricating vertical field effect transistors (VFETs) and vertical diodes on the same substrate with optimal performance and integration, particularly in achieving high-density scaling and controlled electrostatics without compromising gate contact pitch.
Innovation Solution
A method involving the formation of a vertical finFET and vertical diode on the same substrate through epitaxial growth, where fin trenches and diode trenches are etched into the channel layer stack, with dummy layer liners formed by oxidation, allowing for the creation of p-n junctions and integration of semiconductor segments to form a functional VFET and diode structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If vertical transistors are used for scaling to smaller dimensions, then device density and electrostatic control are improved, but fabrication complexity and integration difficulty with diodes increase
Solution Approach 1:
The patent combines the fabrication processes for vertical finFETs and vertical diodes into a single integrated process flow. Both device types share common steps including channel layer formation, trench etching, dummy gate formation, spacer deposition, and epitaxial growth, thereby reducing overall fabrication complexity while achieving high device density
Solution Approach 2:
The fabrication process is designed to be universal, accommodating both finFET and diode structures through the same sequence of operations. The dummy gate layer and spacer structures serve dual purposes for both device types, and the epitaxial growth conditions are optimized to form both vertical fins and diode regions simultaneously
2Area of stationary object
If vertical finFET and vertical diode are co-integrated on the same substrate, then space utilization and device density are improved, but process compatibility and performance optimization become more difficult
Solution Approach 1:
The patent applies local quality by forming different device structures in different regions of the substrate using the same overall process flow. Fin trenches are formed in regions where finFETs are desired, while diode trenches are formed in regions where vertical diodes are desired. The dummy gate layer and spacers are formed uniformly across the substrate but serve different functions in different regions
Solution Approach 2:
The substrate is segmented into different device regions through selective trench formation. The process divides the substrate into finFET regions with vertical fins and diode regions with vertical junctions, allowing both device types to coexist on the same substrate while maintaining optimal performance characteristics for each device type
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the co-integration of VFETs and vertical diodes on a single substrate, enhancing device density and electrostatic control while maintaining gate contact pitch, thus addressing the limitations of existing technologies.
Implementation Method 1
oxidizing at least a portion of the channel layer stack inside the one or more fin trenches to form a dummy layer liner
Implementation Method 2
forming a first semiconductor segment in a lower portion of at least one of the one or more diode trenches with the dummy layer liner; and forming a second semiconductor segment in an upper portion of the at least one of the one or more diode trenches with the first semiconductor segment
Data Source
AI summary
A method of forming a vertical finFET and vertical diode device on the same substrate, including forming a channel layer stack on a heavily doped layer; forming fin trenches in the channel layer stack; oxidizing at least a portion of the channel layer stack inside the fin trenches to form a dummy layer liner; forming a vertical fin in the fin trenches with the dummy layer liner; forming diode trenches in the channel layer stack; oxidizing at least a portion of the channel layer stack inside the diode trenches to form a dummy layer liner; forming a first semiconductor segment in a lower portion of the diode trenches with the dummy layer liner; and forming a second semiconductor segment in an upper portion of the diode trenches with the first semiconductor segment, where the second semiconductor segment is formed on the first semiconductor segment to form a p-n junction.