Vertical Fin E-Fuse with Oxidized Sidewall for Chip Space Reduction
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Solution Overview
Problem
Electrically programmable fuses (e-fuses) consume precious chip space due to their size, limiting the manufacturing yield and functionality of semiconductor chips.
Innovation Solution
A semiconductor structure with a vertical fin having an oxidized sidewall is manufactured, which can be reduced in size by removing the oxidized sidewall, allowing for the formation of a smaller e-fuse that saves chip space, and the vertical fin can be silicided to form an e-fuse with the top and bottom cathode/anode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a conventional e-fuse structure is used, then the fuse functionality is achieved, but the chip space consumption is excessive
Solution Approach 1:
The patent transitions from a planar e-fuse structure to a vertical fin structure that extends in the third dimension (depth). The fin structure rises vertically from the substrate, allowing the fuse element to occupy vertical space rather than only horizontal chip area, thereby reducing footprint while maintaining functionality
Solution Approach 2:
The e-fuse structure is nested within the vertical fin geometry. The fuse element is formed by siliciding the fin structure, with the cathode/anode regions integrated into the fin's vertical architecture. This nesting allows the fuse functionality to be embedded within the fin structure rather than requiring separate dedicated space
2Area of stationary object
If the vertical fin width is reduced to save chip space, then the chip space is conserved, but the manufacturing precision requirements increase
Solution Approach 1:
The patent performs preliminary oxidation of the fin sidewalls before final patterning. This preliminary action creates a controlled oxide layer that serves as a buffer, allowing subsequent etching steps to achieve precise fin width control. The oxidation process occurs at a defined stage in the manufacturing sequence, preparing the structure for high-precision width reduction
Solution Approach 2:
The oxidized sidewall acts as an intermediary layer between the original fin structure and the final reduced-width fin. This oxide layer serves as a sacrificial material that can be selectively removed or thinned to achieve the target fin width with high precision, mediating the transition from larger to smaller dimensions
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The reduced size of the e-fuse structure conserves chip space, enabling the production of semiconductor chips with lower costs and increased functionality.
Implementation Method 1
the vertical fin has an oxidized sidewall
Implementation Method 2
the vertical fin may be silicided to form an e-fuse with the top cathode/anode and the bottom cathode/anode
Data Source
AI summary
The present disclosure provides a method for manufacturing a semiconductor structure having a vertical fin with an oxidized sidewall. The method of manufacturing the semiconductor structure includes the steps of providing a substrate having a bottom source/drain and a bottom cathode/anode; forming a channel fin on the bottom source/drain of the substrate and a vertical fin on the cathode/anode of the substrate; forming a top source/drain on the channel fin and a top cathode/anode on the vertical fin; forming a gate structure on the channel fin; and forming an oxidized sidewall on the vertical fin.