Vertical Fin ESD Protection via Parasitic NPN Junction
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Solution Overview
Problem
Vertical fin technologies in semiconductor devices lack effective electrostatic discharge (ESD) protection due to the absence of a parasitic bipolar NPN junction, making them vulnerable to damage from ESD events.
Innovation Solution
A method is developed to integrate a bipolar parasitic NPN structure beneath the vertical fin, which includes forming n-type and p-type doped active areas on a substrate to create a NPN junction that can handle high voltages and redirect ESD current to ground, thereby protecting the device from damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If vertical fin technology is used to increase device density and scaling, then manufacturing precision and device miniaturization are improved, but electrostatic discharge protection capability deteriorates due to absence of parasitic bipolar NPN junction
Solution Approach 1:
The ESD protection structure is segmented into distinct n-type and p-type doped regions arranged in a specific pattern around the vertical fin, creating multiple NPN junctions that collectively provide protection while maintaining device scaling
Solution Approach 2:
A parasitic bipolar NPN junction is introduced as an intermediary protective structure between the ESD event source and the sensitive vertical fin device, redirecting harmful ESD current through the doped regions to protect the main device
2Reliability
If ESD protection structures are added to vertical fin devices, then reliability against ESD events is improved, but device complexity increases
Solution Approach 1:
The ESD protection structure is merged with the existing vertical fin device architecture by integrating doped regions into the substrate surrounding the fin, allowing dual functionality without separate protection components
Solution Approach 2:
The doped regions serve multiple functions: they create the parasitic NPN junction for ESD protection, maintain electrical connectivity, and preserve the vertical fin's primary switching functionality, reducing the need for additional specialized components
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively provides ESD protection for vertical fin technologies by allowing high voltage handling and redirecting transient ESD currents, preventing damage to input/output devices and maintaining compatibility with existing fabrication processes.
Implementation Method 1
An ESD event can deliver a large amount of energy to the chip, potentially destroying input/output circuitry
Implementation Method 2
forming a first active area and a second active area, each including an n-type dopant, on the substrate at opposing ends of the one or more fins
Data Source
AI summary
A method of fabricating a semiconductor device includes forming one or more fins on a substrate. The method includes forming a first active area and a second active area, each including an n-type dopant, on the substrate at opposing ends of the one or more fins. The method further includes forming a third active area including a p-type dopant on the substrate adjacent to the first active area and the second active area.