Vertical FinFET with Current-Blocking Structure
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Solution Overview
Problem
Existing vertical fin-based transistors face challenges such as limited device density, performance variability due to doping inhomogeneities, and the need for expensive silicon-on-insulator substrates, as well as complex manufacturing processes.
Innovation Solution
A vertical Fin-FET semiconductor device with a current-blocking structure and epitaxially grown vertical semiconductor fins, where the fins have doped bottom and top portions and an undoped channel portion, allowing for efficient doping without thermal treatment or SOI substrates, and enabling sharp doping boundaries and reduced manufacturing steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If isolated vertical nanowires are used to form transistors, then device density is increased, but the cross-sectional area of the channel is limited and device performance deteriorates
Solution Approach 1:
The patent transitions from zero-dimensional nanowire channels to three-dimensional fin structures with extended cross-sectional area. The fin geometry provides a larger channel cross-section compared to nanowires while maintaining vertical orientation, thus improving drive current and device performance without sacrificing the high device density achieved through vertical architecture.
Solution Approach 2:
The patent employs composite material structures including silicon-germanium (SiGe) sacrificial layers combined with silicon fins, and multiple doping layers (n-type and p-type) to create the vertical FinFET structure. This composite approach enables both high device density and improved channel characteristics through material composition optimization.
2Ease of manufacture
If heavily doped silicon is deposited and thermally treated to dope the base portion of the fin, then doping is achieved, but inhomogeneities in the doping profile and diffuse boundaries are introduced leading to performance variability
Solution Approach 1:
The patent incorporates doping elements directly during the epitaxial growth process rather than through subsequent thermal diffusion. This preliminary doping action during growth ensures uniform dopant distribution from the outset and creates sharp, well-defined doping boundaries without the diffusion broadening that occurs with thermal treatment.
Solution Approach 2:
The patent replaces thermal diffusion processes with epitaxial growth-based doping. Instead of using thermal energy to diffuse dopants (which causes profile broadening), the invention uses controlled chemical vapor deposition during epitaxial growth to incorporate dopants uniformly throughout the crystal structure, achieving superior doping homogeneity.
3Ease of manufacture
If SOI substrates are used for forming vertical FinFETs, then device fabrication is enabled, but manufacturing cost increases significantly
Solution Approach 1:
The patent replaces expensive SOI substrates with standard silicon wafers that can be processed using conventional CMOS fabrication techniques. The invention uses epitaxial growth to create the necessary fin structures and doping profiles on inexpensive bulk silicon, eliminating the need for costly SOI substrates while maintaining device performance.
Solution Approach 2:
The patent changes the substrate parameter from SOI (silicon-on-insulator) to bulk silicon, and modifies the processing parameters to use epitaxial growth instead of conventional planar processing. This parameter change enables the use of cheaper substrates while achieving the required three-dimensional fin structures through controlled epitaxial processes.
4Reliability
If multiple processes including trench deposition and thermal treatment are used to dope the fin base, then doping is achieved, but manufacturing complexity and process time increase
Solution Approach 1:
The patent merges the fin formation process and the doping process into a single epitaxial growth step. Instead of separately creating fins through trench etching and then doping them through thermal diffusion, the invention simultaneously grows the fin structure with incorporated dopants during the same epitaxial process, significantly reducing manufacturing steps and time.
Solution Approach 2:
The patent performs doping during the fin formation epitaxial growth process itself, rather than as a subsequent step. This preliminary doping action eliminates the need for separate thermal diffusion processes and reduces overall manufacturing cycle time while ensuring uniform dopant distribution.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in transistors with improved channel volume, electrostatics, and performance, occupying less surface area while reducing manufacturing complexity and costs, and achieving high drive current with minimal device footprint.
Implementation Method 1
The fin and the substrate have each a crystalline structure and said crystalline structures are epitaxially aligned
Data Source
AI summary
A vertical FinFET semiconductor device and a method of forming the same are disclosed. In one aspect, the semiconductor device includes a current-blocking structure formed over a semiconductor structure and a semiconductor fin formed on the current-blocking structure. The current blocking structure includes a first layer of a first conductive type, a layer of a second conductive type over the first layer, and a second layer of the first conductive type over the layer of the second conductive type. The semiconductor fin has a doped bottom portion contacting the current-blocking structure, a doped top portion formed vertically opposite to the doped bottom portion and a channel portion vertically interposed between the doped bottom portion and the doped top portion.