Vertical Fin FET Structure With Graded Doping for Low On-Resistance
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Solution Overview
Problem
Current power transistor devices face challenges with slow switching speeds, high specific on-resistance, and high leakage current, particularly at high voltages, which hinder their performance in power electronics applications.
Innovation Solution
The development of vertical-fin-based FET devices with a graded doping region and an epitaxially regrown ternary III-V compound gate layer on a binary III-V compound substrate, which reduces on-resistance and leakage current by creating a two-dimensional electron gas that facilitates current flow, and the use of a self-aligned source contact to minimize parasitic capacitances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional power transistor devices are used, then high voltage handling capability is achieved, but switching speed is slow and specific on-resistance is high
Solution Approach 1:
The patent transitions from planar transistor architecture to vertical FinFET architecture, adding the vertical dimension for current flow. The fin structure extends the channel vertically, increasing the effective channel area without increasing the device footprint, thereby reducing specific on-resistance while maintaining high voltage capability and enabling faster switching.
Solution Approach 2:
The patent employs graded doping regions that create composite material structures with varying doping concentrations. This graded composition optimizes the balance between on-resistance and breakdown voltage, allowing the device to achieve low specific on-resistance while maintaining high voltage handling capability.
2Reliability
If conventional power transistor devices are used, then high voltage handling capability is achieved, but leakage current is high
Solution Approach 1:
The patent utilizes graded doping regions where the doping concentration gradually changes from the drift region to the fin region. This parameter change optimizes the electric field distribution, reducing peak electric fields that cause breakdown while maintaining low resistance for current flow, thereby reducing leakage current at high voltages.
Solution Approach 2:
The patent applies different doping concentrations to different regions: heavy doping in the drift region for high voltage blocking, graded doping in the transition region for field control, and light doping in the fin channel for low resistance. This local quality optimization simultaneously achieves high breakdown voltage and low leakage current.
3Reliability
If vertical FinFET structure with graded doping is used, then specific on-resistance is reduced and switching speed is improved, but device complexity increases
Solution Approach 1:
The patent incorporates graded doping regions during the epitaxial growth process before fin formation. This preliminary action of creating the graded doping profile in advance simplifies subsequent processing steps and ensures optimal electrical characteristics are built into the structure during fabrication rather than requiring complex post-processing adjustments.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances switching speed, reduces specific on-resistance, and improves breakdown voltage, achieving better performance in power electronics by controlling the etched depth and utilizing polarization-induced strain for efficient current distribution.
Implementation Method 1
The development of vertical-fin-based FET devices with a graded doping region and an epitaxially regrown ternary III-V compound gate layer on a binary III-V compound substrate, which reduces on-resistance and leakage current by creating a two-dimensional electron gas that facilitates current flow
Implementation Method 2
achieving better performance in power electronics by controlling the etched depth and utilizing polarization-induced strain for efficient current distribution
Data Source
AI summary
A method of fabricating a vertical fin-based field effect transistor (FET) includes providing a semiconductor substrate having a first surface and a second surface, the semiconductor substrate having a first conductivity type, epitaxially growing a first semiconductor layer on the first surface of the semiconductor substrate, the first semiconductor layer having the first conductivity type and including a drift layer and a graded doping layer on the drift layer, and epitaxially growing a second semiconductor layer having the first conductivity type on the graded doping layer. The method also includes forming a metal compound layer on the second semiconductor layer, forming a patterned hard mask layer on the metal compound layer, and etching the metal compound layer and the second semiconductor layer using the patterned hard mask layer as a mask exposing a surface of the graded doping layer to form a plurality of fins surrounded by a trench.