Vertical Fin FET Bottom Junction Alignment via Epitaxial Growth
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Solution Overview
Problem
The challenge in fabricating vertical field-effect-transistors (FETs) lies in forming an aligned bottom junction during the fin etching process, as conventional fin etching processes often result in fins with a wider bottom portion, which is not suitable for forming FET channels, especially for technology scaling beyond 5 nm.
Innovation Solution
A method involving the formation of a substrate with a first source/drain layer and pillar structures, followed by epitaxial growth of a doped layer on the fins and pillar structures, and the creation of a gate structure with a dielectric and gate layer, ensuring a self-aligned bottom junction by controlling the growth of the epitaxy layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fin etching processes are used, then the fin etching can be completed, but the fins have a wider bottom portion which is not suitable for forming FET channels
Solution Approach 1:
A sacrificial layer is deposited and patterned before the fin etching process to define the desired fin bottom width. This preliminary structure guides the etching process to stop at the correct location, preventing the formation of wider bottom portions and ensuring proper alignment for subsequent FET channel formation.
Solution Approach 2:
The sacrificial layer acts as an intermediary element during the fin etching process. It temporarily exists to control the etching depth and bottom width, then is removed afterward. This mediator enables precise fin bottom geometry without requiring direct control of the etching stop point.
2Productivity
If technology scaling is pursued beyond 5 nm, then device density is improved, but it becomes difficult to form aligned bottom junctions
Solution Approach 1:
The sacrificial layer is formed in advance with dimensions that define the target fin bottom width. This preliminary structure provides a physical template that ensures proper bottom junction alignment even as device dimensions scale down to 5 nm and below, where conventional etching control becomes insufficient.
Solution Approach 2:
The approach changes the controlling parameter from etching depth control to lateral dimension control through the sacrificial layer. By shifting from vertical etching control to lateral template definition, the method maintains manufacturing precision for bottom junction alignment as devices scale to smaller nodes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the precise formation of vertical fin FETs with a self-aligned bottom junction, addressing the issue of fin width variability and enabling effective channel formation, thus facilitating technology scaling beyond 5 nm.
Implementation Method 1
A doped layer is epitaxially grown from the first source/drain layer in contact with the plurality of fins and the plurality of pillar structures
Data Source
AI summary
A vertical fin field-effect-transistor and a method for fabricating the same. The vertical fin field-effect-transistor includes a substrate, a first source/drain layer including a plurality of pillar structures, and a plurality of fins disposed on and in contact with the plurality of pillar structures. A doped layer epitaxially grown from the first source/drain layer is in contact with the plurality of fins and the plurality of pillar structures. A gate structure is disposed in contact with two or more fins in the plurality of fins. The gate structure includes a dielectric layer and a gate layer. A second source/drain layer is disposed on the gate structure. The method includes epitaxially growing a doped layer in contact with a plurality of fins and a plurality of pillar structures. A gate structure is formed in contact with two or more fins. A second source/drain layer is formed on the gate structure.