Vertical Fin FET Gate Length Variation Reduction
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Solution Overview
Problem
The challenge in forming vertical fin field effect transistors (FinFETs) lies in addressing loading effects that cause tapering gate heights, leading to variations in gate lengths, which complicates the fabrication of smaller device components.
Innovation Solution
The method involves forming dummy fins and dummy fin portions on the perimeter of the substrate region to compensate for loading effects, shifting the tapering effect outward from the active semiconductor portion, thereby reducing gate length variations. This is achieved by creating a fin mesa and an elevated substrate tier surrounded by a fill layer, from which dummy fins and active vertical fins are formed during the fin formation process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If traditional FET structures are used with horizontal current flow, then fabrication is simpler, but device dimensions cannot be scaled down effectively
Solution Approach 1:
The patent transitions from horizontal current flow in planar FETs to vertical current flow in FinFETs. The channel is formed as a vertical fin structure extending from the substrate, with the gate wrapping around the fin sidewalls. This dimensional change enables continued scaling of device dimensions while maintaining effective gate control and manageable fabrication complexity through self-aligned processes.
2Length of moving object
If vertical fin structures are formed, then device scaling is improved, but loading effects cause tapering gate heights and gate length variations
Solution Approach 1:
The patent performs preliminary actions by forming dummy fins and dummy fin portions before forming the actual gate structure. These dummy structures are created to compensate for the loading effects that will occur during gate formation. By pre-positioning these compensatory structures, the tapering effect is shifted outward from the active fin region, ensuring uniform gate lengths across all active fins while maintaining the benefits of vertical device scaling.
3Manufacturing precision
If dummy fins are formed on substrate perimeter, then gate length variations are reduced, but device complexity increases
Solution Approach 1:
The patent introduces dummy fins and dummy fin portions as intermediary structures that mediate between the fabrication process requirements and the final device performance. These intermediary structures serve as placeholders that absorb loading effects during gate formation, protecting the active fins from tapering. After gate formation, the dummy structures can be removed or retained as isolation features, having served their primary purpose of ensuring gate length uniformity without permanently increasing active device complexity.
Data Source
AI summary
A method of forming a fin field effect transistor is provided. The method includes forming an elevated substrate tier on a substrate, and forming a fin mesa on the elevated substrate tier with a fin template layer on the fin mesa, wherein the elevated substrate tier is laterally larger than the fin mesa and fin template layer. The method includes forming a fill layer on the substrate, wherein the fill layer surrounds the fin mesa, elevated substrate tier, and fin template layer, forming a plurality of fin masks on the fill layer and fin template layer, and removing portions of the fill layer, fin template layer, and fin mesa to form a plurality of dummy fins from the fill layer, one or more vertical fins from the fin mesa, and a dummy fin portion on opposite ends of each of the one or more vertical fins from the fill layer.