Vertical Transport Fin FETs with Self-Aligned Isolation and Air Gap
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Solution Overview
Problem
As device dimensions decrease, forming individual components and electrical contacts in Field Effect Transistors (FETs) becomes increasingly difficult due to scaling issues, particularly with channel lengths and gate dielectric thicknesses, requiring a method to retain positive aspects of traditional FET structures while overcoming these challenges.
Innovation Solution
The method involves forming vertical transport fin FETs with self-aligned dielectric separators using protective spacers and sacrificial liners on vertical fins to align a deep isolation region without increasing fin spacing, incorporating an insulating plug with a pinch-off void to reduce parasitic capacitance and maintain isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional FET structures are used with decreasing device dimensions, then manufacturing difficulty increases, but device performance must be maintained
Solution Approach 1:
The patent transitions from planar FET structures to vertical transport fin FETs, utilizing the third dimension (vertical orientation) to maintain effective channel length and gate control while allowing larger lateral pitch. This dimensional change enables continued scaling without proportionally reducing all dimensions, thus maintaining manufacturing feasibility while preserving device performance.
Solution Approach 2:
The methodology employs preliminary patterning and protective spacer formation before final isolation region definition. The protective spacers are formed first to establish reference structures, then the isolation regions are aligned to these spacers, ensuring precise positioning without requiring additional alignment steps during subsequent processing.
2Ease of manufacture
If fin spacing is increased to facilitate isolation region formation, then device density decreases, but manufacturing complexity is reduced
Solution Approach 1:
The protective spacers serve dual functions: they act as structural elements during fabrication and as self-aligned masks for defining the isolation regions. The spacers automatically position the isolation regions at the correct locations between fins without requiring separate alignment operations, enabling precise isolation formation at standard fin pitches.
Solution Approach 2:
The methodology combines the protective spacer function with the alignment reference function. The same protective spacer structure that protects the fin during processing also serves as the template for defining the isolation region boundaries, eliminating the need for separate alignment references and reducing overall process complexity.
3Manufacturing precision
If additional processing steps are added for precise alignment, then manufacturing precision improves, but device complexity increases
Solution Approach 1:
The protective spacers automatically define the isolation region locations through their physical presence and geometry. The isolation regions are formed by etching or depositing materials aligned to the spacer structures, which self-align due to their conformal formation on the fins. This self-alignment mechanism achieves high precision without requiring additional lithography alignment steps.
Solution Approach 2:
The protective spacers are formed in advance as preliminary structures that establish the geometric framework for subsequent isolation region definition. By having these reference structures in place before isolation formation, the patent enables precise alignment to be achieved through simple physical alignment to the spacers rather than complex multi-step lithographic alignment.
Data Source
AI summary
A method of forming a vertical transport fin field effect transistor with self-aligned dielectric separators, including, forming a bottom source/drain region on a substrate, forming at least two vertical fins on the bottom source/drain region, forming a protective spacer on the at least two vertical fins, forming a sacrificial liner on the protective spacer, forming an isolation channel in the bottom source/drain region and substrate between two of the at least two vertical fins, forming an insulating plug in the isolation channel, wherein the insulating plug has a pinch-off void within the isolation channel, and forming the dielectric separator on the insulating plug.