Vertical FinFET T-Shaped Gate Leakage Current
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Solution Overview
Problem
As transistors shrink, they experience increased leakage current, leading to battery drainage and heat buildup in semiconductor chips, which existing technologies have not adequately addressed.
Innovation Solution
A vertical fin field effect transistor (V-FinFET) is developed with a T-shaped fin structure and a gate insulating layer, along with work-function-control patterns and a gate electrode, to reduce leakage current through a specific etching and deposition process, controlling the gate length and transistor operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistor size is reduced to increase integration density, then productivity and device density improve, but leakage current increases causing energy loss and heat generation
Solution Approach 1:
The patent transitions from planar transistor architecture to vertical FinFET architecture, moving the channel conduction path from a two-dimensional plane to a three-dimensional vertical fin structure. This dimensional change allows for better gate control over the channel while maintaining smaller footprint, thereby increasing integration density without proportionally increasing leakage current. The vertical fin structure provides a longer effective channel length within a smaller planar area, improving device density while the gate's wrap-around control reduces off-state leakage.
2Productivity
If transistor size is reduced to increase integration density, then productivity improves, but heat generation increases due to higher leakage current
Solution Approach 1:
By adopting vertical FinFET architecture, the patent achieves better heat dissipation characteristics. The vertical fin structure increases the surface area-to-volume ratio, improving thermal coupling with the substrate and surrounding structures. This enhanced thermal management capability allows higher integration density without proportional increases in heat generation, as the vertical structure provides more efficient heat pathways compared to planar devices.
Solution Approach 2:
The patent modifies key geometric parameters of the transistor structure, including fin height, fin width, and gate wrap-around angle, to optimize the balance between integration density and heat generation. By carefully controlling these parameters, the design achieves high device density while maintaining acceptable thermal characteristics through improved heat dissipation pathways provided by the vertical architecture.
3Ease of manufacture
If conventional planar transistor structure is used, then manufacturing process is simple, but leakage current control is insufficient
Solution Approach 1:
The patent implements vertical FinFET architecture with gate wrap-around structure, where the gate electrode extends around the sidewalls of the fin structure. This three-dimensional gate configuration provides superior electrostatic control over the channel compared to planar structures, significantly reducing off-state leakage current. The wrap-around gate ensures better field control at the channel interface, improving reliability without requiring fundamentally new manufacturing approaches, as it can be achieved through adapted standard semiconductor fabrication processes.
Data Source
AI summary
A vertical fin field effect transistor (V-FinFET) is provided as follows. A T-shaped fin structure extend vertically from an upper surface of a substrate. The T-shaped fin structure includes a lower part and an upper part. The lower part is in contact with the upper surface of the substrate. The upper part of the T-shaped fin structure is vertically stacked on the lower part of the T-shaped fin structure. A gate insulating layer surrounds the lower part. A work-function-control pattern surrounds the lower part. The gate insulating layer is interposed between the work-function-control pattern and the lower part of the T-shaped fin structure. A gate electrode is disposed on a sidewall of the work-function-control pattern.