Vertical Fin FET Self-Aligned Source Drain Junctions
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Solution Overview
Problem
Current FinFET technologies face challenges in achieving self-aligned source/drain junctions with controlled gate-to-source/drain overlap, which is crucial for efficient device performance and scaling in logic and memory devices.
Innovation Solution
The method involves forming vertical fins on a substrate with a doped layer and a self-aligned gate structure, using a semi-sacrificial doped layer to ensure self-aligned gate-to-source/drain overlap junctions, and controlling the position of source/drain junctions through dopant diffusion and layer formation processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional FinFET fabrication methods are used, then horizontal current flow is achieved, but self-aligned source/drain junctions with controlled gate-to-source/drain overlap cannot be formed
Solution Approach 1:
The patent transitions from horizontal current flow in conventional FinFETs to vertical current flow through upright fins extending from the substrate. This dimensional change enables self-aligned source/drain junctions where the source and drain regions are positioned at different heights along the vertical fin structure, achieving precise alignment control that is not possible with horizontal configurations.
Solution Approach 2:
The method forms the source and drain regions before completing the gate structure. Specifically, bottom source/drain regions are formed at the base of the fin, followed by formation of top source/drain regions at the fin apex, with the gate structure subsequently formed between them. This preliminary action sequence enables self-alignment of the source/drain junctions to the gate edges.
2Ease of manufacture
If source and drain are formed in the substrate with horizontal current flow, then simple fabrication is achieved, but controlled gate-to-source/drain overlap and self-aligned junctions are not possible
Solution Approach 1:
The invention moves from planar horizontal current flow to vertical current flow through upright fins. This allows source and drain regions to be positioned at different vertical levels (bottom source/drain at the substrate interface, top source/drain at the fin apex), enabling self-aligned junctions with controlled overlap while maintaining fabrication feasibility through sequential processing steps.
3Reliability
If vertical fins are formed with self-aligned source/drain junctions, then device performance and scalability are improved, but complex multi-step fabrication processes are required
Solution Approach 1:
The source/drain structure is segmented into distinct bottom source/drain regions and top source/drain regions, with the gate structure forming between them. This segmentation allows independent formation and optimization of each region, enabling self-aligned junctions with controlled gate-to-source/drain overlap while managing fabrication complexity through modular processing steps.
Solution Approach 2:
The bottom source/drain regions are formed preliminarily before the gate structure, followed by formation of the gate, and then the top source/drain regions are formed to complete the self-aligned junctions. This preliminary action sequence enables precise alignment control despite the multi-step nature of the process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of FinFET devices with self-aligned source/drain junctions and controlled gate-to-source/drain overlap, improving device performance and scalability for applications in logic and memory circuits.
Implementation Method 1
growing a doped layer on the bottom source/drain layer and sidewalls of the plurality of vertical fins
Data Source
AI summary
A method of forming a fin field effect transistor device is provided. The method includes forming a plurality of vertical fins on a substrate. The method further includes forming a bottom source/drain layer adjacent to the plurality of vertical fins, and growing a doped layer on the bottom source/drain layer and sidewalls of the plurality of vertical fins. The method further includes forming a dummy gate liner on the doped layer and the bottom source/drain layer, and forming a dummy gate fill on the dummy gate liner. The method further includes forming a protective cap layer on the dummy gate fill, and removing a portion of the protective cap layer to expose a top surface of the plurality of vertical fins.