Vertical FinFET Gate Dielectric Segmentation for Leakage Suppression
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Solution Overview
Problem
FINFETs on bulk substrates face leakage issues due to punch-through current, which is suppressed by punch-through stop implants, but these implants degrade carrier mobility and introduce non-uniformities, making them undesirable.
Innovation Solution
A method involving forming a high dielectric constant gate dielectric and L-shaped metal stacks on the fins, separated by a low dielectric constant layer, reducing parasitic capacitance and addressing leakage issues without degrading carrier mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If punch-through stop implant is used to suppress leakage current, then drain to source current is reduced, but carrier mobility is degraded and within-fin non-uniformities are introduced
Solution Approach 1:
The gate dielectric is segmented into two distinct portions: a first portion with high dielectric constant (k>4.0) positioned over the substrate and between fins, and a second portion with low dielectric constant (k<4.0) conformally lining the metal stack sidewalls. This segmentation allows the high-k portion to suppress punch-through leakage while the low-k portion maintains uniform electrical characteristics and prevents within-fin non-uniformities, thereby resolving the contradiction between leakage suppression and carrier mobility uniformity.
Solution Approach 2:
Different dielectric materials are applied to different spatial locations within the gate structure. The high-k dielectric is locally positioned in the region between fins where punch-through suppression is most critical, while the low-k dielectric is locally positioned on the metal stack sidewalls where uniform electrical field distribution is needed. This local quality differentiation enables simultaneous achievement of leakage suppression and uniform carrier mobility.
2Reliability
If high dielectric constant gate dielectric is used, then parasitic capacitance increases, but carrier mobility is improved
Solution Approach 1:
The gate dielectric structure employs local quality differentiation by positioning high-k dielectric material specifically in regions where capacitance reduction is critical (between fins and over substrate) while using low-k dielectric material in regions where high carrier mobility is needed (conformally on metal stack sidewalls). This spatially differentiated dielectric configuration simultaneously achieves low parasitic capacitance and high carrier mobility without the traditional trade-off.
Solution Approach 2:
The gate dielectric is constructed as a composite structure combining two different dielectric materials with contrasting properties: a high-k dielectric (k>4.0) and a low-k dielectric (k<4.0). This composite configuration leverages the high-k material's ability to reduce parasitic capacitance while using the low-k material's beneficial electrical characteristics to maintain high carrier mobility, thereby resolving the contradiction between these two parameters.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces parasitic capacitance and minimizes the impact on carrier mobility, improving the performance of FINFETs on bulk substrates by creating a structured dielectric and metal stack configuration.
Implementation Method 1
the first gate dielectric has a dielectric constant above approximately 4.0
Implementation Method 2
the first dielectric layer has a dielectric constant below approximately 4.0
Data Source
AI summary
The disclosure is directed to an integrated circuit structure and methods of forming the same. The integrated circuit structure may include: a set of fins within an ILD layer on a substrate; a first gate dielectric over the substrate and extending along opposing sidewalls of each fin in the set of fins, a metal stack adjacent to the first gate dielectric and on the opposing sidewalls of each fin, the metal stack having a first portion over the substrate and a second portion contacting the first gate dielectric and extending along the opposing sidewalls of each fin, wherein at least the first portion of the metal stack and a portion of the first gate dielectric above the substrate is replaced by another dielectric material; a set of epitaxial regions within the ILD layer; and a conductor within the ILD layer and extending over each epitaxial region.