Vertical Fin Sidewall Interfacial Layering to Prevent VTFET Re-Growth
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Solution Overview
Problem
Conventional semiconductor fabrication techniques face challenges in scaling down devices to smaller sizes, particularly in forming uniform interfacial layers on vertical fin sidewalls of vertical transport field-effect transistors (VTFETs), leading to issues like interfacial layer re-growth and charge trapping, which degrade gate stack reliability.
Innovation Solution
A method involving patterning a hard mask layer, forming vertical fins, trimming their sidewalls, and creating a uniform interfacial layer on these sidewalls to prevent re-growth, using techniques such as chemical oxidation and conformal deposition, while forming a gate stack and spacers to maintain layer integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If conventional fabrication techniques are used to form interfacial layers on vertical fin sidewalls, then device scaling is achieved, but interfacial layer re-growth and charge trapping occur degrading reliability
Solution Approach 1:
The patent applies preliminary action by forming the interfacial layer on the vertical fin sidewalls before subsequent processing steps that could cause damage. The method specifically forms the interfacial layer after creating the vertical fins and before forming the gate stack, preventing re-growth and charge trapping that would otherwise occur during later fabrication steps. This timing ensures the interfacial layer is established in a controlled state before exposure to conditions that could degrade it.
2Reliability
If interfacial layer is formed on vertical fin sidewalls, then device performance is enhanced, but fabrication complexity increases
Solution Approach 1:
The patent merges the formation of the interfacial layer with the existing vertical fin fabrication process. The interfacial layer is formed as an integrated step within the sequence of creating vertical fins, forming spacers, and constructing gate stacks. This consolidation avoids adding significant fabrication complexity while achieving enhanced device performance through the presence of the interfacial layer.
3Ease of manufacture
If conventional methods are used without trimming, then manufacturing is simpler, but interfacial layer uniformity is poor leading to re-growth
Solution Approach 1:
The patent applies preliminary action by trimming the vertical fin sidewalls before forming the interfacial layer. This trimming step prepares the sidewalls with uniform geometry, ensuring that the subsequently formed interfacial layer achieves uniform thickness and composition. By addressing the sidewall geometry in advance, the method prevents non-uniformity that would lead to re-growth while maintaining manufacturing feasibility.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures a uniform interfacial layer on VTFETs, enhancing device performance by preventing re-growth and damage, thereby improving the reliability and efficiency of VTFETs.
Implementation Method 1
forming an interfacial layer on the trimmed sidewalls of the second portion of the one or more vertical fins
Implementation Method 2
forming a top spacer on sidewalls of the hard mask layer and the first portion of the one or more vertical fins
Data Source
AI summary
A method of forming a semiconductor structure includes patterning a hard mask layer over a top surface of a substrate. The method also includes forming a first portion of one or more vertical fins below the patterned hard mask layer. The method further includes forming a top spacer on sidewalls of the hard mask layer and the first portion of the one or more vertical fins. The method further includes forming a second portion of the one or more vertical fins in the substrate below the top spacer and trimming sidewalls of the second portion of the one or more vertical fins. The method further includes forming an interfacial layer on the trimmed sidewalls of the second portion of the one or more vertical fins. The one or more vertical fins provide one or more vertical transport channels for one or more vertical transport field-effect transistors.