Vertical Fin Inverter Architecture for Higher Transistor Density
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Solution Overview
Problem
The challenge in semiconductor device manufacturing is the difficulty in scaling transistor pitch and increasing transistor density due to constraints in lithographic processes, which leads to increased gate capacitance and dynamic energy consumption, particularly in achieving the '2 *Endcap + End-to-End Spacing' parameters for gate and trench contact endcap regions.
Innovation Solution
The approach involves a vertical integration scheme and circuit elements architecture that fabricates entire circuit elements on a single semiconductor fin, eliminating the need for mask registration and allowing self-aligned gate endcap and trench contact overlap, thereby reducing the complexity of lithographic patterning and increasing transistor density without scaling the pitch.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional lithographic processes are used to pattern semiconductor features, then manufacturing precision can be maintained, but transistor pitch scaling becomes difficult and transistor density increases only slowly
Solution Approach 1:
The patent transitions from planar 2D transistor arrangement to vertical 3D stacking architecture. Multiple transistor layers are stacked vertically with source/drain regions extending through intermediate layers, enabling higher transistor density without requiring advanced lithographic patterning for horizontal placement. The vertical dimension provides additional space for device integration while maintaining manufacturability with existing lithography tools.
2Productivity
If transistor dimensions are reduced to increase density, then more devices fit on chip, but gate capacitance and dynamic energy consumption increase
Solution Approach 1:
By stacking transistors vertically, the patent achieves higher device capacity without further reducing horizontal transistor dimensions. This maintains optimal gate capacitance characteristics while increasing overall chip capacity through the vertical dimension. The source/drain regions extending through intermediate layers enable efficient current paths that reduce resistive losses.
Solution Approach 2:
The patent merges multiple transistor layers into a compact vertical stack with shared source/drain regions. This consolidation reduces the total gate area required compared to planar arrangements, thereby reducing total gate capacitance while maintaining high device capacity through vertical integration.
3Manufacturing precision
If mask registration is required for precise gate and trench contact alignment, then manufacturing precision is maintained, but process complexity and cost increase
Solution Approach 1:
The patent employs self-aligned fabrication where gate structures and trench contacts automatically align through the vertical stacking process without requiring separate mask registration steps. The intermediate layers and source/drain region formation provide inherent alignment references, eliminating complex lithographic alignment procedures while maintaining precise gate endcap and trench contact positioning.
Data Source
Figure 1
Figure 2A~2B
Figure 3A~3B
AI summary
Vertical integration schemes and circuit elements architectures for area scaling of semiconductor devices are described. In an example, an inverter structure includes a semiconductor fin separated vertically into an upper region and a lower region. A first plurality of gate structures is included for controlling the upper region of the semiconductor fin. A second plurality of gate structures is included for controlling the lower region of the semiconductor fin. The second plurality of gate structures has a conductivity type opposite the conductivity type of the first plurality of gate structures.