Vertical FinFET Transistor Leakage Current Reduction
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Solution Overview
Problem
As transistors shrink, they experience increased leakage current, leading to battery drainage and heat buildup in semiconductor chips, which existing technologies have not adequately addressed.
Innovation Solution
A vertical field effect transistor (FinFET) design is implemented, featuring a fin structure with a gate electrode surrounding the center sidewall region, and overlapping upper and lower source/drain configurations to manage current flow and reduce leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistor size is reduced to increase integration density, then productivity is improved, but leakage current increases causing battery drainage and heat buildup
Solution Approach 1:
The patent transitions from planar 2D channel structures to vertical 3D FinFET structures. The fin structure extends vertically from the substrate surface, creating a three-dimensional channel that increases the effective channel area and integration density while maintaining better electrostatic control to reduce leakage current in scaled devices
Solution Approach 2:
The gate electrode completely surrounds the fin structure in a wrap-around configuration, with the gate wrapping around the channel from front, back, and sidewalls. This nested gate structure provides enhanced electrostatic control over the channel, effectively suppressing leakage current while maintaining compact device footprint
2Productivity
If transistor size is reduced to increase integration density, then productivity is improved, but heat buildup increases
Solution Approach 1:
The vertical FinFET structure distributes current flow and heat generation across three dimensions rather than confining them to a planar 2D area. The vertical fin extends the channel length in the z-direction, increasing surface area for heat dissipation while maintaining compact lateral footprint, thus reducing heat buildup in high-density integrations
3Ease of manufacture
If planar transistor structure is used to simplify manufacturing, then ease of manufacture is improved, but leakage current control deteriorates
Solution Approach 1:
The gate electrode is segmented into multiple regions: front gate, back gate, and sidewall gates that wrap around the fin structure. This segmentation allows independent control of different channel regions, providing superior leakage current suppression compared to single-planar gates while using standard semiconductor fabrication techniques
Data Source
AI summary
A vertical field effect transistor is provided as follows. A substrate has a lower drain and a lower source arranged along a first direction in parallel to an upper surface of the substrate. A fin structure is disposed on the substrate and extended vertically from the upper surface of the substrate. The fin structure includes a first end portion and a second end portion arranged along the first direction. A bottom surface of a first end portion of the fin structure and a bottom surface of a second end portion of the fin structure overlap the lower drain and the lower source, respectively. The fin structure includes a sidewall having a lower sidewall region, a center sidewall region and an upper sidewall region. A gate electrode surrounds the center side sidewall region of the fin structure.