Vertical Fin S/D Contact Structure for Scalable Transistor Performance
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Solution Overview
Problem
Existing vertical field-effect transistors have not been satisfactory in all aspects, particularly in terms of performance and scalability as the semiconductor industry continues to advance.
Innovation Solution
A method of fabricating a semiconductor component involving the formation of fins on a substrate, followed by the deposition of a dielectric layer and a capping layer. Gate structures are then formed over the fins, and epitaxial layers are grown to enhance carrier mobility. Additional epitaxial contact portions are formed to prevent deactivation, and silicides are formed to improve device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional planar metal-oxide-semiconductor field-effect transistors are used, then manufacturing is simpler, but device performance and scalability are insufficient
Solution Approach 1:
The patent transitions from conventional planar (2D) transistor structures to vertical (3D) field-effect transistor structures by forming fins that extend vertically from the substrate. This dimensional change increases the effective channel area and improves device performance while enabling better scalability as feature sizes decrease.
Solution Approach 2:
The transistor structure is segmented into distinct vertical regions including the fin, gate structure, source/drain regions, and contact structures. This segmentation allows each component to be optimized independently for its specific function while maintaining overall device performance.
2Productivity
If feature size is decreased to increase interconnected devices per unit area, then circuit density increases, but manufacturing precision requirements increase
Solution Approach 1:
By moving to vertical transistor structures, the patent achieves higher device density per unit area without proportionally decreasing horizontal feature sizes. The vertical dimension provides additional space for multiple interconnected devices while maintaining manufacturable feature dimensions.
3Adaptability or versatility
If vertical field-effect transistors are implemented, then scalability improves, but existing designs have performance deficiencies
Solution Approach 1:
The patent applies different materials and structures to different regions of the vertical transistor. For example, the fin may have different doping concentrations at different heights, the gate structure may use different materials for different functions, and contact structures may be optimized for specific electrical characteristics. This local optimization improves overall device performance while maintaining scalability.
Solution Approach 2:
The vertical transistor structure employs composite materials including semiconductor fins, dielectric layers, metal gates, and doped regions. These composite structures enable simultaneous optimization of electrical performance, mechanical stability, and scalability across different device sizes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The described method improves the performance and scalability of semiconductor components by enhancing carrier mobility and preventing deactivation, leading to more efficient and reliable semiconductor devices.
Implementation Method 1
epitaxial layers are grown to enhance carrier mobility
Implementation Method 2
silicides are formed to improve device performance
Data Source
AI summary
A semiconductor device includes a semiconductor channel region, a source/drain region, and a contact structure. The semiconductor channel region is over a substrate. The source/drain region is adjacent the semiconductor channel region. The source/drain region has a notched corner. The contact structure has a portion inlaid in the notched corner in the source/drain region.