Vertical Fin Transistor Anchor Layer for Stable Junctions
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Solution Overview
Problem
During the fabrication of vertical fin-shaped field effect transistors (VFETs), it is challenging to form an aligned bottom junction due to uncertainties in etching stopping at the edge of highly doped source/drain layers, leading to stability issues with wide top portions and small fin bottom channels, which can result in instability and sharp junctions.
Innovation Solution
The method involves forming vertical fins on a semiconductor substrate with a hardmask, depositing an anchor layer, and creating an angled recessed region for the bottom source/drain formation, which provides stability during the source/drain recess and bottom lateral etching process, ensuring precise placement and sharp junctions between the sigma-shaped source/drain and fin channel.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional VFET fabrication methods are used, then device density is improved, but fin stability deteriorates due to uncertainties in etching stopping at the edge of highly doped source/drain layers
Solution Approach 1:
The patent applies preliminary action by forming a sacrificial layer and defining a bottom source/drain region before completing the fin formation process. This preliminary structuring provides a reference framework that ensures etching stops at the correct position, preventing fin instability while maintaining high device density through efficient space utilization.
Solution Approach 2:
The patent introduces a sacrificial layer as an intermediary element that mediates between the etching process and the final fin structure. This sacrificial layer acts as a temporary structure that guides the etching process to stop at the precise edge of the highly doped source/drain layers, ensuring fin stability without compromising device density.
2Ease of manufacture
If wide top portions and small fin bottom channels are formed, then manufacturing is simplified, but device performance deteriorates due to instability and sharp junctions
Solution Approach 1:
The patent applies local quality by creating different fin geometries at different locations: wide top portions for structural stability and control, and precisely controlled bottom channels for optimal electrical performance. The bottom source/drain region definition ensures that the fin channel width is locally optimized at the bottom while maintaining easier manufacturing through the overall sigma shape.
Solution Approach 2:
The patent uses preliminary action to define the bottom source/drain region and form the sacrificial layer before completing fin formation. This preliminary structuring establishes the correct bottom channel dimensions and prevents sharp junctions, while the overall simplified sigma-shaped geometry maintains ease of manufacture.
3Device complexity
If etching is performed without precise control, then manufacturing complexity is reduced, but junction sharpness deteriorates leading to poor electrostatics and high external resistance
Solution Approach 1:
The patent introduces a sacrificial layer as an intermediary that enables precise etching control without significantly increasing process complexity. This sacrificial layer acts as a physical stop marker during etching, ensuring sharp junctions are formed at the bottom source/drain region while keeping the overall manufacturing process relatively simple.
Solution Approach 2:
The patent applies preliminary action by pre-defining the bottom source/drain region and forming the sacrificial layer before the critical etching step. This preliminary preparation ensures that when etching occurs, it stops precisely at the intended location, creating sharp junctions with good electrostatics without requiring complex real-time etching control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the stability and performance of VFETs by maintaining fin stability and achieving sharp junctions, improving electrostatics and reducing external resistance, thereby addressing the limitations of existing VFET fabrication techniques.
Implementation Method 1
depositing an anchor layer in the opening
Implementation Method 2
depositing a liner layer on sidewalls of each of the vertical fins
Data Source
AI summary
A method for fabricating a semiconductor structure is provided. The method includes forming one or more vertical fins on a semiconductor substrate with a hardmask on a top surface of the one or more vertical fins. The method includes forming an opening in the hardmask and the one or more vertical fins and in a portion of the semiconductor substrate to form a plurality of vertical fins. The method includes depositing an anchor layer in the opening. The method includes depositing a liner layer on sidewalls of each of the vertical fins and above a top surface of the semiconductor substrate. The method includes forming an angled recessed region in the exposed portion of each of the vertical fins below the liner layer and in the semiconductor substrate. The method includes forming a bottom source/drain region in the angled recessed region.