Vertical Fin Transistor Composite High-K Low-K Spacers
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Solution Overview
Problem
Vertical fin field effect transistor devices face challenges in achieving optimal top source/drain junctions due to parasitic capacitances and resistance issues, which are not adequately addressed by existing technologies.
Innovation Solution
The method involves forming a composite high-K and low-K spacer around the vertical fin and top source/drain, creating a cavity and grooves to enhance gate coupling and reduce parasitic capacitance, while using a gate spacer with both high-K and low-K portions to improve the top junction without requiring a replacement metal gate process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional gate structure is used, then the device structure is simple, but parasitic capacitance is high and top junction performance is poor
Solution Approach 1:
The gate structure is segmented into multiple functional components: a gate electrode, a gate dielectric layer, and a composite spacer system with high-K and low-K regions. This segmentation allows each component to perform its specific function optimally, reducing parasitic capacitance while maintaining manageable complexity through modular design
Solution Approach 2:
The spacer structure implements local quality by using high-K dielectric material in specific regions (near the fin) to enhance coupling, and low-K dielectric material in other regions (away from the fin) to reduce parasitic capacitance. This spatial variation of material properties optimizes top junction performance without requiring complete structural redesign
2Reliability
If high-K spacer is used throughout, then gate coupling is enhanced, but parasitic capacitance increases
Solution Approach 1:
The composite spacer structure applies high-K dielectric material locally in regions where enhanced gate coupling is beneficial (adjacent to the fin), while using low-K dielectric material in regions where parasitic capacitance would be problematic (away from the fin). This spatial differentiation resolves the contradiction by optimizing both coupling and capacitance reduction in their respective locations
Solution Approach 2:
The spacer is constructed as a composite structure combining high-K and low-K dielectric materials. This composite approach allows the structure to simultaneously provide enhanced gate coupling (through the high-K region) and reduced parasitic capacitance (through the low-K region), resolving the contradiction between these two opposing requirements
3Reliability
If replacement metal gate process is used, then top junction performance improves, but manufacturing complexity and thermal budget increase
Solution Approach 1:
The invention changes the dielectric constant parameter of the spacer material rather than changing the gate electrode material. By using a composite high-K/low-K spacer structure with conventional silicon gates, the method achieves improved top junction performance while avoiding the complexity and high thermal budget associated with replacement metal gate processes
Data Source
AI summary
A method of forming a vertical fin field effect transistor device is provided. The method includes forming a vertical fin and fin template on a bottom source/drain layer, wherein the fin template is on the vertical fin. The method further includes forming a gate structure on the vertical fin and fin template, and forming a top spacer layer on the gate structure. The method further includes removing the fin template to form an opening in the top spacer layer, and removing a portion of a gate electrode of the gate structure to form a cavity; and removing a portion of a gate dielectric layer of the gate structure to form a groove around the vertical fin.