Vertical Fin Transistors for 3D IC Layer Alignment
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Solution Overview
Problem
Conventional methods for fabricating 3D monolithic semiconductor IC devices require fine lithographic alignment and connections between upper and lower device layers, which is challenging and inefficient.
Innovation Solution
A method involving the formation of vertical fin structures with insulating spacers and sacrificial layers to fabricate vertical field-effect transistor devices, allowing for the separation and processing of p-type and n-type FET devices on different layers without the need for precise alignment, by encapsulating semiconductor fins in sacrificial insulating material and bonding additional substrates for device layer formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional bonding methods are used to connect upper and lower device layers, then device integration is achieved, but fine lithographic alignment is required which increases manufacturing complexity and reduces productivity
Solution Approach 1:
The patent divides the device into separate upper and lower layers that are processed independently on different substrates. The lower device layer is formed on a first substrate while the upper device layer is formed on a second substrate, allowing each layer to be manufactured separately without requiring precise alignment during the formation process. This segmentation eliminates the need for fine lithographic alignment between layers.
Solution Approach 2:
The patent introduces bonding pads and bonding interconnects as intermediary elements that facilitate connection between the upper and lower device layers. These bonding elements serve as mediators that enable electrical connection without requiring direct alignment between active devices on different layers, thus simplifying the manufacturing process.
2Reliability
If conventional bonding methods are used to connect upper and lower device layers, then device integration is achieved, but connections between layers require precise alignment which reduces productivity
Solution Approach 1:
By segmenting the device into independently processable upper and lower layers on separate substrates, the patent enables parallel processing of different device layers. This segmentation allows each layer to be fabricated, tested, and prepared for bonding independently, significantly improving fabrication efficiency while maintaining reliable device integration through subsequent bonding of the layers.
3Adaptability or versatility
If p-type and n-type FET devices are separated on different layers, then optimal semiconductor materials can be used for each device type, but additional substrate bonding and alignment steps are required
Solution Approach 1:
The patent segments p-type and n-type FET devices onto different device layers that can be formed on separate substrates. This segmentation enables the use of optimal semiconductor materials for each device type (e.g., germanium for n-type, silicon-germanium for p-type) without requiring complex heteroepitaxial growth or material compatibility considerations, thereby maintaining material optimization while simplifying the overall manufacturing process.
Data Source
AI summary
Devices and methods are provided for fabricating vertical field-effect transistor devices for monolithic three-dimensional semiconductor integrated circuit devices. A semiconductor structure is formed to include a substrate and a stack of layers formed on the substrate including a first active semiconductor layer, an insulating layer, and a second active semiconductor layer. A vertical fin structure is formed by patterning the first and second active semiconductor layers and the insulating layer, wherein the vertical fin structure includes first and second vertical semiconductor fins, and an insulating fin spacer disposed between the first and second vertical semiconductor fins. The first and second vertical semiconductor fins are utilized to fabricate first and second vertical field-effect transistor devices on first and second device layers of a monolithic three-dimensional semiconductor integrated circuit device.