Vertical FinFET-GAA Structure for High-Density Semiconductor Layouts
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Solution Overview
Problem
Current semiconductor devices face challenges in achieving high device density and performance due to limitations in three-dimensional design and fabrication processes, particularly in forming nanostructure transistors and FinFET devices with precise gate structures and isolation.
Innovation Solution
The method involves forming a semiconductor device structure with a FinFET device integrated with a nanostructure GAA device, using sacrificial layers, epitaxial growth, and precise patterning techniques to create stacked horizontal GAA devices with multiple gate structures and nanostructures, and employing inner and outer gate spacers for isolation and device stacking.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensional designs are used to increase device density, then device density is improved, but fabrication complexity increases
Solution Approach 1:
The fabrication process is divided into distinct stages: forming sacrificial layers, depositing semiconductor layers, patterning gates, and removing sacrificial materials. Each stage handles a specific aspect of the three-dimensional structure formation, making the complex fabrication process more manageable and repeatable
Solution Approach 2:
Sacrificial layers are formed in advance before the actual device structures are built. These preliminary structures guide the formation of gates and nanostructures, and are removed later to create the final three-dimensional configuration, simplifying the overall fabrication sequence
2Area of stationary object
If FinFET and GAA devices are stacked vertically, then layout area is reduced, but manufacturing precision requirements increase
Solution Approach 1:
Multiple device structures are nested vertically within the same footprint area. FinFET devices and GAA devices are stacked one above another, with each device type occupying different vertical levels, thereby reducing the horizontal layout area while maintaining manufacturing precision through controlled deposition and patterning processes
Solution Approach 2:
The design transitions from two-dimensional lateral arrangement to three-dimensional vertical stacking. By utilizing the vertical dimension for device placement, the layout area is significantly reduced while precision is maintained through advanced lithography and atomic-layer deposition techniques
3Reliability
If multiple gate structures are formed around nanostructures, then device performance is enhanced, but fabrication difficulty increases
Solution Approach 1:
Sacrificial layers serve as intermediary structures during fabrication. These temporary layers enable the formation of complex gate structures around nanostructures by providing a mold or template, and are removed after the gates are formed, simplifying the overall manufacturing process while achieving the desired multi-gate configuration
Solution Approach 2:
The sacrificial layers act as protective cushions during the fabrication process, allowing precise formation of gate structures without directly contacting or damaging the underlying nanostructures. This preliminary protection enables complex three-dimensional gate formation while maintaining ease of manufacture
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for increased device density and reduced layout area by isolating and stacking FinFET and GAA devices vertically, enhancing performance and efficiency in semiconductor devices.
Implementation Method 1
a first semiconductor stack is formed over the first sacrificial layer, and a second semiconductor stack is formed over the second sacrificial layer
Data Source
AI summary
A semiconductor device structure is provided. The semiconductor device structure includes a first device formed over a substrate, wherein the first device includes a first fin structure and a first S/D structure formed over the first fin structure. The semiconductor device structure includes a second device formed over or below the first device, and the second device includes a plurality of second nanostructures stacked in a vertical direction. The semiconductor device structure also includes a second S/D structure formed over the second nanostructures, and the second S/D structure is directly above or below the first S/D structure.