Vertical FinFET Layout for Lower Gate-to-S/D Parasitic Capacitance
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Solution Overview
Problem
In the manufacturing of semiconductor integrated circuits, the existing shallow-trench-isolation (STI) process results in unwanted parasitic capacitance between the gate and bottom source/drain regions of vertical transistors due to gaps between the vertical ends of fins and the edge of the bottom source/drain regions, affecting the operational speed of transistors as they are scaled to smaller nodes.
Innovation Solution
The transistor structure is designed with a bottom source/drain region that extends horizontally beyond the vertical fin, aligning its edge with the vertical end, and includes a shallow-trench-isolation region and a bottom spacer adjacent to the edge, ensuring the STI region extends between adjacent transistors, reducing parasitic capacitance. The method involves forming raw vertical fins, patterning the source/drain regions, cutting the fins, creating STI regions, and forming additional features to optimize the transistor structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the STI region is formed using conventional manufacturing processes, then the fabrication process is simple, but the STI region is not immediately adjacent to the vertical ends of the fins, resulting in increased parasitic capacitance
Solution Approach 1:
The patent performs preliminary actions by forming the bottom source/drain regions to extend beyond the fin edges before forming the STI region. This preliminary extension of the S/D regions creates the necessary geometry that allows the STI to be formed immediately adjacent to the fin vertical ends, thereby reducing parasitic capacitance while maintaining a manageable manufacturing process
Solution Approach 2:
The patent applies local quality by creating a non-uniform geometry where the bottom source/drain regions extend horizontally beyond the vertical fin edges at specific locations. This localized extension allows the STI region to be positioned immediately adjacent to the fin vertical ends, reducing parasitic capacitance in the critical area without requiring global process changes
2Speed
If the bottom source/drain region is positioned to reduce parasitic capacitance, then operational speed improves, but the device structure becomes more complex
Solution Approach 1:
The patent merges the function of the bottom source/drain region with the isolation structure by having the S/D region extend horizontally beyond the fin edges and combine with the STI region. This merging creates a unified structure that provides both electrical connection and parasitic capacitance reduction, improving operational speed without proportionally increasing device complexity
Data Source
AI summary
Embodiments of present invention provide a transistor structure. The transistor structure includes a first vertical fin of a first vertical transistor, the first vertical fin having a first and a second sidewall and a first and a second vertical end; a first bottom source/drain (S/D) region underneath the first vertical fin, wherein the first bottom S/D region having an edge that vertically aligns with the first vertical end of the first vertical fin; and a first gate stack surrounding the first vertical fin, wherein the first bottom S/D region horizontally extends beyond the first vertical fin, except at the edge of the first bottom S/D region that vertically aligns with the first vertical end of the first vertical fin, to have at least a portion vertically underneath the first gate stack. A method of manufacturing the transistor structure is also provided.