Vertical FinFET Self-Aligned Contact Spacing
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Solution Overview
Problem
Aggressive scaling of semiconductor devices leads to challenges such as parasitic capacitance and short circuits due to decreased spacing between conductive elements in vertical FinFETs, which affects device performance and reliability.
Innovation Solution
A method for forming vertical FinFETs involves creating a semiconductor fin with a bottom source/drain region, a gate stack over the fin's sidewalls, and a self-aligned contact structure that allows for reduced spacing between source/drain contacts and the fin, using a sidewall spacer to isolate contacts and enable closer proximity to the fin, thereby improving manufacturability and yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If aggressive scaling is applied to reduce device footprint, then device density improves, but parasitic capacitance and short circuits increase due to decreased spacing between conductive elements
Solution Approach 1:
The patent transitions from planar contact geometry to a vertical/dimensional contact structure that extends underneath the gate. The contact is formed in a trench that goes through the gate stack and reaches the bottom source/drain region, utilizing the vertical dimension to achieve closer spacing without increasing lateral parasitic capacitance.
Solution Approach 2:
The patent introduces a dielectric layer as an intermediary between the contact and the gate stack. This dielectric layer is conformally deposited over the gate stack and sidewalls, providing electrical isolation and preventing short circuits while allowing the contact to be positioned closer to the fin structure.
2Length of moving object
If spacing between source/drain contacts and fin is reduced to improve scaling, then device density improves, but short circuit risk increases
Solution Approach 1:
The contact structure moves from a lateral positioning approach to a vertical trench approach. The contact is formed by etching through the gate stack vertically, allowing the contact opening to be positioned directly over the bottom source/drain region while maintaining lateral spacing through the gate stack's physical presence.
Solution Approach 2:
The gate stack itself acts as an intermediary barrier between the contact and the fin. The conformal dielectric layer deposited over the gate stack provides additional insulation, ensuring that even when the contact is laterally close to the fin, electrical isolation is maintained through the gate stack structure.
3Manufacturing precision
If self-aligned contact structure is formed closer to the fin, then manufacturing precision improves, but process complexity increases
Solution Approach 1:
The gate stack serves as a self-aligning reference structure for contact formation. The conformal dielectric layer is deposited uniformly over the gate stack and sidewalls, and the contact trench is etched using the gate stack as a lateral boundary. This self-aligned approach eliminates the need for separate alignment steps and reduces dependence on lithographic precision.
Solution Approach 2:
The gate stack is formed first as a preliminary structure that defines the lateral boundaries for subsequent contact formation. The conformal dielectric layer is deposited in advance over the gate stack, creating a pre-defined isolation structure that guides the contact etching process and ensures proper positioning.
Data Source
AI summary
A vertical FinFET includes a semiconductor fin formed over a semiconductor substrate. A self-aligned first source/drain contact is electrically separated from a second source/drain contact by a sidewall spacer that is formed over an endwall of the fin. The sidewall spacer, which comprises a dielectric material, allows the self-aligned first source/drain contact to be located in close proximity to an endwall of the fin and the associated second source/drain contact without risk of an electrical short between the adjacent contacts.