Vertical FinFETs With Protective Inner Spacer Liner
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Solution Overview
Problem
Current methods for forming vertical finFET devices face challenges in scaling down device components, particularly in forming the drain, channel, and source regions, which leads to increased fin exposure to erosion during the spacer recess etch, limiting the modularity and precision of fin structure width.
Innovation Solution
The method involves forming a low-k spacer material and an inner spacer liner on the semiconductor material, followed by epitaxial growth of the channel semiconductor material, and selective etching to create a recessed spacer structure that protects the fin structures during the spacer recess etch, allowing for greater control over the fin structure width and reduced erosion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If traditional FET structures are used with horizontal current flow, then device scaling is simpler, but device dimensions cannot be reduced further due to scaling limits
Solution Approach 1:
The patent transitions from horizontal current flow in planar FETs to vertical current flow in finFET structures. The channel extends outward from the substrate in a vertical orientation, allowing current to flow vertically through the fin structure. This dimensional change enables continued scaling of device dimensions while maintaining manufacturability through established epitaxial growth and etching processes.
2Productivity
If device dimensions are reduced to improve scaling, then productivity increases, but fin exposure to erosion during spacer recess etch increases
Solution Approach 1:
The patent forms an inner spacer liner on the sidewalls of fin structure openings before performing the spacer recess etch. This preliminary protective layer is deposited conformally to protect the fin structures from erosion during the subsequent etching process. The inner spacer liner acts as a sacrificial or protective layer that prevents direct exposure of the fin structures to the etchant, thereby reducing fin erosion while enabling continued device scaling.
Solution Approach 2:
The inner spacer liner serves as an intermediary layer between the fin structures and the etchant during the spacer recess process. This intermediate layer mediates the interaction by providing a protective barrier that prevents the etchant from directly attacking the fin structures, thereby reducing erosion while still allowing the spacer recess to be formed.
3Ease of manufacture
If inner spacer liner is completely removed to expose channel semiconductor material, then gate formation is simplified, but fin structure protection is lost
Solution Approach 1:
The patent applies selective removal of the inner spacer liner in different regions. The liner is removed in areas where gate formation requires direct access to the channel semiconductor material, while retaining the liner in areas where fin structure protection is needed. This localized quality approach allows the process to optimize for both gate formation simplicity and fin structure integrity in different spatial locations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the modularity of fin structure width and reduces erosion, enabling more precise and scalable fabrication of vertical finFET devices while maintaining the positive aspects of traditional FET structures.
Implementation Method 1
The inner spacer liner is removed selectively to the channel semiconductor material
Implementation Method 2
Channel semiconductor material is then epitaxially formed on the surface of the first semiconductor material
Data Source
AI summary
A method of fabricating a vertical field effect transistor comprising that includes forming openings through a spacer material to provide fin structure openings to a first semiconductor material, and forming an inner spacer liner on sidewalls of the fin structure openings. A channel semiconductor material is epitaxially formed on a surface of the first semiconductor material filling at least a portion of the fin structure openings. The spacer material is recessed with an etch that is selective to the inner spacer liner to form a first spacer. The inner spacer liner is removed selectively to the channel semiconductor material. A gate structure on the channel semiconductor material, and a second semiconductor material is formed in contact with the channel semiconductor material.