Vertical Flash-Cell Neuromorphic Element for Dense Analog Computing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current neural network implementations, particularly in software and digital CMOS processors, are inefficient due to complex digital computations required for artificial neurons, which involve multiple floating-point multiplications and additions.
Innovation Solution
A neuromorphic device is developed for analog computation, featuring a vertical stack of flash-like cells with a common control gate and individually contacted source-drain regions, enabling non-volatile programming and efficient layout resource utilization, allowing for fast evaluation and programming.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If digital CMOS implementation is used for neural networks, then universality and adaptability are improved, but device complexity and computational efficiency deteriorate
Solution Approach 1:
The patent replaces digital CMOS computational systems with an analog neuromorphic device that directly mimics neuronal behavior. The floating-gate transistor structure enables continuous voltage control to represent synaptic weights, eliminating the need for complex digital floating-point arithmetic circuits. This substitution of digital mechanical/computational systems with analog physical systems reduces circuit complexity while maintaining neural network adaptability.
Solution Approach 2:
The patent utilizes the continuous voltage parameter of the floating-gate transistor to represent synaptic weights, enabling analog computation. By changing the control parameter from discrete digital values to continuous analog voltages, the system achieves efficient neural network computation without requiring complex digital circuitry, thus reducing device complexity while preserving versatility.
2Measurement precision
If digital floating-point operations are used, then computational precision is improved, but processing speed and energy efficiency deteriorate
Solution Approach 1:
The patent implements continuous analog voltage computation instead of discrete digital operations. The floating-gate transistor allows continuous adjustment of synaptic weights through voltage control, enabling parallel analog computation of multiple neural operations simultaneously. This continuous action eliminates the sequential processing bottleneck of digital floating-point operations, dramatically improving computation speed while maintaining sufficient precision for neural network applications.
3Area of stationary object
If vertical stacking is implemented, then area utilization is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent transitions from planar two-dimensional transistor layout to three-dimensional vertical stacking. By stacking multiple floating-gate transistors vertically with shared control gates, the system achieves high-density integration that dramatically reduces the area required for neural network implementation. This dimensional transition from 2D to 3D space allows efficient use of layout resources while the standard semiconductor fabrication processes maintain achievable manufacturing precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution provides a compact, high-density implementation of artificial neurons, reducing circuit complexity by using analog memory for computations, enabling nanosecond processing times with fewer devices compared to standard CMOS implementations.
Implementation Method 1
a first floating-gate transistor on the substrate, the first floating-gate transistor having: a channel; a floating gate; and a control gate
Implementation Method 2
a gate contact connected to: the control gate of the first floating-gate transistor; and the control gate of the second floating-gate transistor
Data Source
AI summary
A neuromorphic device for the analog computation of a linear combination of input signals, for use, for example, in an artificial neuron. The neuromorphic device provides non-volatile programming of the weights, and fast evaluation and programming, and is suitable for fabrication at high density as part of a plurality of neuromorphic devices. The neuromorphic device is implemented as a vertical stack of flash-like cells with a common control gate contact and individually contacted source-drain (SD) regions. The vertical stacking of the cells enables efficient use of layout resources.