Vertical Floating Body Cell With Surrounding Gate
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Solution Overview
Problem
The existing floating body cell (FBC) technology faces challenges in reducing transistor size due to limited charge accumulation area and high manufacturing costs associated with the use of silicon-on-insulator (SOI) wafers, which hinder the integration and data retention of semiconductor devices.
Innovation Solution
A semiconductor device with a tube-type channel and a surrounding gate structure is developed, featuring a bias electrode connected to the semiconductor substrate and an insulating film between the channel and electrode, allowing for efficient charge accumulation and data retention without the need for a SOI wafer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a plane transistor structure is used in FBC, then the device can be fabricated with simpler process, but the charge accumulation area is reduced and data retention time decreases
Solution Approach 1:
The patent transitions from a planar transistor structure to a vertical tube-type channel structure. This dimensional change from 2D to 3D allows the channel to extend vertically through multiple layers, significantly increasing the charge accumulation area while maintaining fabrication feasibility through sequential layer formation processes.
Solution Approach 2:
The patent implements a nested structure where the tube-type channel is surrounded by a gate electrode, which is in turn surrounded by an insulating film. This nested arrangement maximizes the use of vertical space, allowing the gate to control the channel from all directions while the insulating film provides electrical isolation, thereby enhancing charge accumulation capability without increasing lateral footprint.
2Productivity
If the channel length is reduced to shrink transistor size, then integration density increases, but the charge accumulation area is reduced and charges are recombined into source/drain regions
Solution Approach 1:
The patent extends the channel in the vertical dimension rather than reducing its length in the lateral dimension. The tube-type channel provides a long vertical path for charge carriers while maintaining a compact lateral footprint, thus achieving both high integration density and sufficient charge accumulation area simultaneously.
Solution Approach 2:
The patent employs a composite structure consisting of the tube-type channel, insulating film, and gate electrode working together. The insulating film prevents charge recombination with the substrate, while the surrounding gate electrode confines and accumulates charges within the channel, creating a synergistic system that enhances charge retention despite reduced lateral dimensions.
3Reliability
If SOI wafer is used to retain holes in the channel bottom, then data retention is improved, but manufacturing costs increase
Solution Approach 1:
The patent creates an artificial SOI-like structure by forming an insulating film beneath the tube-type channel through standard semiconductor fabrication processes. This copied structure replicates the charge retention functionality of expensive SOI wafers using cost-effective materials and processes, achieving the same electrical isolation and charge confinement effects without the high material costs.
Solution Approach 2:
The patent replaces expensive SOI wafers with inexpensive insulating film materials that can be deposited using conventional CVD or PECVD processes. Although the insulating film serves a critical function, the material itself is low-cost and can be integrated into standard manufacturing flows, dramatically reducing wafer costs while maintaining device performance.
4Reliability
If a capacitor is connected to the cell transistor in DRAM, then data storage is enabled, but the device structure becomes complicated and integration is hindered
Solution Approach 1:
The patent merges the storage function traditionally performed by a separate capacitor into the transistor structure itself. The tube-type channel with surrounding gate and insulating film creates an inherent charge accumulation region that eliminates the need for an external capacitor, thereby simplifying the overall device structure while maintaining data storage capability.
Solution Approach 2:
The tube-type channel structure serves multiple functions simultaneously: it acts as the current conduction path, the charge accumulation region, and the control element for data storage. This multi-functional design eliminates the need for separate dedicated storage components, reducing device complexity and enabling higher integration densities.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances integration and data retention time while reducing manufacturing costs, enabling the creation of highly integrated semiconductor devices with improved read/write operation speeds and signal-to-noise ratios.
Implementation Method 1
The FBC structure utilizes a floating body effect phenomenon that changes a threshold voltage when charges are accumulated in a channel bottom of the transistor
Implementation Method 2
A surrounding gate electrode is formed over the tube-type channel
Implementation Method 3
A bias electrode connected to a semiconductor substrate in the tube-type channel
Data Source
AI summary
A semiconductor device includes a tube-type channel formed over a semiconductor substrate. The tube-type channel is connected to first and second conductive lines. A bias electrode is formed in the tube-type channel. The bias electrode is connected to the semiconductor substrate. An insulating film is disposed between the tube-type channel and the bias electrode. A surrounding gate electrode is formed over the tube-type channel.