Vertical Floating Gate NOR Memory Cell for Uniform Trench Depth
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Solution Overview
Problem
The fabrication of nonvolatile semiconductor memory cells, such as NOR memory cells, is complex and inefficient, particularly due to difficulties in forming uniform trench depths in the substrate, which affects the uniformity of memory cell operation across the wafer.
Innovation Solution
The method improves fabrication efficiency by combining certain deposition steps for peripheral logic transistor gates and memory cell gates, and by depositing less oxide in the vicinity of trenches, thereby enhancing trench depth uniformity and memory cell operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If many masks and processing steps are used to fabricate memory cells, then the memory cell structure can be formed, but the fabrication process complexity increases and efficiency decreases
Solution Approach 1:
The patent combines multiple separate deposition steps into a single deposition process. Specifically, the control gate electrode and the first electrode are deposited simultaneously in one step, eliminating the need for separate masks and processing steps for each electrode formation. This merging approach maintains the required structural precision while significantly reducing process complexity
Solution Approach 2:
The patent employs a multi-functional electrode structure where the control gate electrode and first electrode are formed in an integrated manner. This universal structure serves multiple functions: it provides the control gate function, establishes the first electrode connection, and simplifies the fabrication process by reducing the number of discrete components that need to be formed separately
2Shape
If thick oxide layers are etched to form trenches, then the trench structure is created, but trench depth uniformity deteriorates across the wafer
Solution Approach 1:
The patent applies local quality by forming the control gate electrode and first electrode with different local properties within the same structure. The control gate electrode portion extends over the trench while the first electrode is positioned differently, allowing each region to have optimized characteristics for its specific function while maintaining overall trench depth uniformity
Solution Approach 2:
The patent transitions from a two-dimensional planar electrode arrangement to a three-dimensional vertical structure. The control gate electrode extends vertically over the trench, and the first electrode is positioned at a different vertical level, utilizing the vertical dimension to resolve the trench formation challenge while maintaining depth uniformity
3Reliability
If separate deposition steps are used for peripheral logic transistor gates and memory cell gates, then each gate can be optimized, but fabrication efficiency decreases
Solution Approach 1:
The patent merges the deposition of peripheral logic transistor gates and memory cell gates into a single deposition step. The control gate electrode and first electrode are formed simultaneously, allowing both gate types to be optimized while significantly improving fabrication efficiency by reducing the number of processing steps
Solution Approach 2:
The patent performs preliminary action by pre-forming the control gate electrode structure before subsequent processing steps. This preliminary structure serves as a foundation for both the memory cell operation and the peripheral logic transistor gates, allowing optimizations to be built upon a already-established base
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies and improves the control of the memory cell fabrication process, leading to more uniform memory cell operation across the wafer and increased manufacturing efficiency.
Implementation Method 1
combining certain deposition steps when forming peripheral logic transistor gates and memory cell gates... depositing less oxide in the vicinity of trenches
Data Source
Figure 1A
Figure 1B~1C
Figure 1D
AI summary
An electrically erasable programmable nonvolatile memory cell includes a semiconductor substrate having a first substrate region and a trench region apart from the first substrate region in a lateral direction, a channel region between the first substrate region and the bottom portion of the trench region, an electrically conductive control gate insulated from and disposed over the first channel portion, an electrically conductive floating gate insulated from the bottom and sidewall portions of the trench region, an insulation region disposed over the second channel portion between the control gate and the second floating gate portion, an electrically conductive source line insulated from the floating gate and electrically connected to the trench region of the substrate, and an electrically conductive erase gate insulated from and disposed over a tip of the floating gate.