Vertical Fuse OTP Memory Cell Layout for Higher Density
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Solution Overview
Problem
Conventional one-time program (OTP) memory devices have low device density due to the use of planar field effect transistors, which occupy large areas and reduce the number of devices per substrate area, and require two transistors per memory cell, increasing manufacturing costs.
Innovation Solution
The implementation of a vertical fuse OTP memory cell design, where each memory cell consists of a single vertical fuse OTP transistor without a read transistor, sharing a vertical gate electrode to increase device density and reduce costs, with the transistors being operated selectively using source-lines, bit-lines, and word-lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If planar field effect transistors are used in OTP memory cells, then the transistors can be manufactured with conventional processes, but the device density is low due to large area occupation
Solution Approach 1:
The patent transitions from planar (2D) transistor architecture to vertical (3D) transistor architecture. The vertical fuse OTP transistor extends in the vertical direction with source-line and bit-line arranged vertically, allowing multiple transistors to be packed into a smaller footprint area while maintaining conventional manufacturing compatibility.
2Reliability
If two transistors per memory cell are used (read transistor and fuse transistor), then reliable read and write operations can be performed, but manufacturing costs increase
Solution Approach 1:
The patent combines the read transistor and fuse transistor functions into a single vertical fuse OTP transistor. The device integrates both read and write operations in one transistor structure, eliminating the need for separate read and fuse transistors, thereby reducing manufacturing complexity and cost while maintaining operational reliability.
Solution Approach 2:
The vertical fuse OTP transistor serves multiple functions: it acts as both the read transistor and the fuse transistor. The same device structure enables both read operations (through controlled current flow) and write operations (through fuse breaking), providing multi-functionality that reduces the number of components needed per memory cell.
3Area of moving object
If vertical fuse OTP transistors are used to increase device density, then more devices can be packed per substrate area, but manufacturing complexity increases
Solution Approach 1:
The vertical fuse OTP transistor structure is segmented into distinct functional regions: source-line, channel structure, bit-line, and gate electrode. This segmentation allows each component to be formed using specialized processes optimized for that structure type, simplifying the overall manufacturing approach despite the vertical architecture.
Data Source
AI summary
In some embodiments, the present disclosure relates to a one-time program memory device that includes a source-line arranged over a bottom dielectric layer. Further, a bit-line is arranged directly over the source-line in a first direction. A channel isolation structure is arranged between the source-line and the bit-line. A channel structure is also arranged between the source-line and the bit-line and is arranged beside the channel isolation structure in a second direction perpendicular to the first direction. A vertical gate electrode extends in the first direction from the bottom dielectric layer to the bit-line and is arranged beside the channel isolation structure in the second direction. The one-time program memory device further includes a gate dielectric layer arranged between the vertical gate electrode and the bit-line, the source-line, and the channel structure.