Vertical Ga2O3 Power FET Structure for >1 kV Breakdown

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing high power Ga2O3 transistors have not achieved breakdown voltages greater than 1 kV, limiting their high voltage and high current operation capabilities.

Innovation Solution

The development of high power vertical gallium oxide (Ga2O3) transistors with a substrate, an n-type Ga2O3 drift layer, a fin-shaped or nanowire-shaped semiconducting channel, and a conductive gate layer, allowing for both depletion and enhancement mode operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If lateral Ga2O3 MOSFETs with field plates are used, then breakdown voltage reaches 750 V, but breakdown voltage cannot exceed 1 kV

Engineering Contradiction:
Improvebreakdown voltageVSAvoidhigh voltage operation capability
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The patent transitions from lateral channel configuration to vertical channel configuration, changing the dimensional orientation of current flow and electric field distribution. This vertical architecture enables breakdown voltages exceeding 1 kV by utilizing the vertical drift layer structure, which provides more efficient voltage blocking capability compared to lateral designs

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent modifies key structural parameters including drift layer thickness (5-20 μm), doping concentration (10^15-10^17 atoms/cm³), and channel dimensions to optimize breakdown voltage. By adjusting these parameters in the vertical device structure, breakdown voltages greater than 1 kV are achieved while maintaining high current density

Inventive Principle:
Principle #35Parameter changes

2Reliability

If Ga2O3 material is used, then wide bandgap enables high voltage operation, but fabrication process compatibility with existing GaN vertical transistor processes is poor

Engineering Contradiction:
Improvehigh voltage operation capabilityVSAvoidfabrication process compatibility
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The patent optimizes Ga2O3 layer parameters including thickness (5-20 μm for drift layer), doping concentration (10^15-10^17 atoms/cm³), and crystal orientation to achieve both high voltage operation and compatibility with existing semiconductor fabrication processes. These parameter adjustments enable the material to exhibit both superior electrical properties and manufacturability

Inventive Principle:
Principle #35Parameter changes

3Power

If vertical Ga2O3 device structure is implemented, then high current density (>1 kA/cm²) and high voltage (>1 kV) operations are enabled, but device complexity increases

Engineering Contradiction:
Improvehigh power operation capabilityVSAvoidvertical device structure complexity
Core Design Contradiction:
PowerVSDevice complexity

Solution Approach 1:

The vertical device is segmented into distinct functional layers: drift layer, active layer, and contact layer, each with specific doping concentrations and thicknesses. This segmentation allows independent optimization of each layer for its specific function while maintaining overall device simplicity and manufacturability

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The vertical Ga2O3 device structure serves multiple functions simultaneously: the drift layer provides voltage blocking, the active layer enables high current conduction, and the overall structure supports both high voltage and high current operations. This multi-functionality reduces the need for additional components, thereby managing complexity

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS12243921B2Vertical gallium oxide (GA2O3) power FETs
Publication Date: 2025.03.04 CORNELL UNIVERSITY
  • US12243921B2 patent drawing
  • US12243921B2 patent drawing
  • US12243921B2 patent drawing

AI summary

A vertical gallium oxide (Ga2O3) device having a substrate, an n-type Ga2O3 drift layer on the substrate, an, n-type semiconducting channel extending from the n-type Ga2O3 drift layer, the channel being one of fin-shaped or nanowire shaped, an n-type source layer disposed on the channel; the source layer has a higher doping concentration than the channel, a first dielectric layer on the n-type Ga2O3 drift layer and on sidewalls of the n-type semiconducting channel, a conductive gate layer deposited on the first dielectric layer and insulated from the n-type source layer, n-type semiconducting channel as well as n-type Ga2O3 drift layer, a second dielectric layer deposited over the conductive gate layer, covering completely the conductive gate layer on channel sidewalls and an ohmic source contact deposited over the n-type source layer and over at least a part of the second dielectric layer; the source contact being configured not to be in electrical contact with the conductive gate layer.