Vertical GAA Transistor Layout With Backside Power Routing
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Solution Overview
Problem
The scaling down of transistor gate lengths leads to short-channel effects such as drain-induced barrier lowering and degradation of sub-threshold slope, compromising the control of current flow and degrading transistor performance, which existing multi-gate transistor architectures like FinFETs and Vertical Gate All Around (VGAA) transistors aim to mitigate but require further improvements.
Innovation Solution
The formation of double-side powered vertical transistors with a vertical Gate-All-Around (GAA) configuration, where both VDD and VSS power lines are formed on the front and backside of the transistors, reducing chip area occupied by transistors and enhancing electrostatic control of the channel, thereby reducing short-channel effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If gate length is scaled down to increase switching speed, then switching speed is improved, but short-channel effects worsen
Solution Approach 1:
The patent transitions from planar 2D gate control to 3D vertical gate-all-around structure, where the gate electrode completely surrounds the channel region in three dimensions. This dimensional change provides superior electrostatic control over the channel, effectively suppressing short-channel effects while maintaining scaled-down gate lengths for high switching speed.
Solution Approach 2:
The gate electrode is positioned within and completely surrounds the channel region, with the gate dielectric layer nested between them. This nested configuration allows the gate to control the channel from all directions, maximizing electrostatic control and minimizing short-channel effects.
2Reliability
If vertical Gate-All-Around (VGAA) transistor structure is used to improve electrostatic control, then short-channel effects are reduced, but chip area occupied increases
Solution Approach 1:
By moving from horizontal planar transistors to vertical standing transistors, the channel extends in the vertical dimension rather than horizontal. This allows multiple channels to be packed closer horizontally, increasing transistor density and reducing the horizontal chip area required while maintaining excellent electrostatic control through the vertical gate-all-around structure.
Solution Approach 2:
The substrate is divided and removed to reveal the bottom surfaces of the vertical channel structures, allowing independent access and optimization of each vertical transistor unit. This segmentation enables compact packaging and efficient use of chip area.
3Area of stationary object
If substrate is removed to reveal bottom surface for backside power connection, then chip area is reduced, but manufacturing complexity increases
Solution Approach 1:
The substrate is selectively divided into separate regions, with portions removed to expose the bottom surfaces of the vertical channel structures. This segmentation allows backside power connections to be made directly to the source/drain regions without requiring complex through-silicon vias or additional interconnection layers, actually simplifying the overall manufacturing process while reducing chip area.
Solution Approach 2:
Instead of making all power connections from the front side of the chip, the patent inverts the approach by making power connections from the backside substrate surface. This inversion allows power distribution to be achieved more directly and with fewer process steps.
Data Source
AI summary
A method includes forming a vertical transistor, and the method includes forming a vertical semiconductor bar over a substrate, forming a gate dielectric and a gate electrode encircling the vertical semiconductor bar, forming a first source/drain region over a top surface of the vertical semiconductor bar, removing the substrate to reveal a bottom surface of the vertical semiconductor bar; and forming a second source/drain region contacting the bottom surface of the vertical semiconductor bar. The method further includes forming a backside power line, with the backside power line being on a bottom side of the vertical semiconductor bar. The backside power line is connected to the second source/drain region.