Vertical GAA Transistor Cell Layout for Dense Semiconductor Integration
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Solution Overview
Problem
Semiconductor devices face challenges in achieving high integration, reliability, and multi-functionality while maintaining low fabrication costs, requiring innovative designs that enhance electrical characteristics and integration capabilities.
Innovation Solution
A semiconductor device with a multi-height cell structure, featuring vertical transistors with gate-all-around architecture, where active patterns and gate electrodes are strategically arranged to improve electrical performance, and a method of fabrication that includes epitaxial growth and dielectric layer formation to enhance transistor characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multi-height cell structure with vertical transistors is implemented, then electrical characteristics and integration are improved, but device complexity increases
Solution Approach 1:
The patent implements vertical transistors that extend in the vertical dimension rather than conventional planar transistors. The active patterns extend vertically from the substrate, and gate electrodes wrap around these vertical structures, utilizing the third dimension to increase integration density and improve electrical characteristics while managing device complexity through spatial reorganization.
Solution Approach 2:
The gate-all-around architecture nests the gate electrode structure around the vertical active patterns. The gate electrode wraps around the channel region in a nested configuration, allowing multiple functional layers to be integrated in a compact vertical arrangement, thereby improving electrical characteristics without proportionally increasing overall device footprint.
2Reliability
If gate-all-around architecture is used, then electrical characteristics are improved, but manufacturing precision requirements increase
Solution Approach 1:
The fabrication process performs preliminary actions by first forming the vertical active patterns and channel structures before wrapping the gate electrode around them. The gate electrode is deposited and patterned to conformally cover the vertical active patterns, ensuring proper alignment and electrical characteristics while managing manufacturing precision through sequential processing steps.
Solution Approach 2:
The gate electrode is formed with a curved, wraparound configuration that conforms to the vertical active patterns. This curved geometry allows the gate to surround the channel region uniformly, improving electrical characteristics by ensuring consistent gate control while the conformal deposition process manages the manufacturing precision requirements for the curved structure.
Data Source
AI summary
A semiconductor device includes a substrate with a first active region; first and second active patterns extending in a first direction and spaced apart in a second direction, and each having a source pattern, a channel pattern, and a drain pattern that are sequentially stacked; first and second gate electrodes that surround the channel patterns of the first and second active patterns and extend in the first direction; an interlayer dielectric layer that covers the first and second active patterns and the first and second gate electrodes; a first active contact that penetrates the interlayer dielectric layer and is coupled to the first active region between the first and second active patterns; and a first power rail on the interlayer dielectric layer and electrically connected to the first active contact, each of the first and second active patterns including an overlapping region that vertically overlaps the first power rail.