Vertical Gate-All-Around Transistor Layout for Tighter Cell Scaling
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Solution Overview
Problem
In advanced technology nodes, the increased gate-drain capacitance and larger metal gate endcap, along with larger source/drain epitaxy sizes, lead to challenges in scaling down integrated circuit cell dimensions and increasing complexity in processing and manufacturing.
Innovation Solution
The formation of a vertical nanostructure transistor with a stack of semiconductor layers of different material concentrations, allowing for precise control and definition of inner spacers and gate electrodes, reduces active area spacing and enables more efficient use of integrated circuit area, simpler source/drain contact formation, and minimizes damages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If conventional planar transistor structures are used, then manufacturing processes are simpler, but integrated circuit cell dimensions cannot be scaled down effectively
Solution Approach 1:
The patent transitions from planar two-dimensional transistor structures to three-dimensional vertical nanosheet structures. The channel region is formed as a vertical nanosheet extending from the substrate surface into the substrate, enabling scaling of cell dimensions by utilizing the vertical dimension for channel length while maintaining lateral space for other circuit elements.
Solution Approach 2:
The patent implements gate electrodes that wrap around and surround the vertical nanosheet channel region, creating a gate-all-around structure. This nested configuration where the gate encloses the channel from multiple directions provides enhanced control over the channel while maintaining compact cell dimensions.
2Reliability
If gate-all-around structures with larger metal gate endcaps are used, then channel control is improved, but gate-drain capacitance increases
Solution Approach 1:
The gate electrode extends vertically along the nanosheet and wraps around it in a three-dimensional configuration. This vertical wrapping approach provides comprehensive channel control from top, bottom, and sidewalls, improving reliability while the compact vertical footprint reduces the horizontal extent of the gate endcap that would otherwise increase capacitance.
3Reliability
If larger source/drain epitaxy sizes are used, then device performance is improved, but active area spacing increases
Solution Approach 1:
The source and drain regions are positioned at the bottom of the vertical nanosheet structure, adjacent to where the nanosheet extends into the substrate. This vertical integration allows sufficient source/drain region size for device performance while minimizing the lateral footprint and active area spacing.
4Manufacturing precision
If vertical nanosheet structures with gate-all-around are fabricated, then manufacturing precision is improved, but device structure complexity increases
Solution Approach 1:
The fabrication process segments the formation of the vertical nanosheet transistor into distinct sequential steps: forming the nanosheet, depositing gate dielectric, forming inner spacers, depositing gate electrode material, and planarization. Each step builds upon the previous one, allowing precise control of dimensions and properties while managing overall device complexity through systematic process decomposition.
Data Source
AI summary
A method for forming vertical gate all around transistors includes forming stack of semiconductor layers on a lower source/drain region. The stack of semiconductor layers includes a first layer, a second layer on the first layer, and a third layer on the second layer. The first and third layers have substantially identical compositions and are selectively etchable with respect to the second layer. The first and second layers can be selectively removed and replaced with inner spacers. The second layer can be selectively removed and replaced with a gate electrode.