Vertical GAA FeRAM Cells for High-Density Logic-Memory Integration
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Solution Overview
Problem
The semiconductor industry faces challenges in achieving high integration density and performance with the incorporation of logic circuits and non-volatile memory circuits within a single chip, particularly as device feature sizes continue to decrease.
Innovation Solution
The development of a semiconductor device structure featuring a vertical-type gate-all-around (GAA) ferroelectric random-access memory (FeRAM) circuit with a ferroelectric material layer between the gate and channel region, enabling high-density memory cell arrays in a Back-End-Of-Line (BEOL) structure, utilizing a dual damascene process for interconnect formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If device feature sizes continue to decrease to achieve higher integration density, then device density improves, but manufacturing precision and reliability deteriorate
Solution Approach 1:
The patent transitions from planar 2D memory cell structures to vertical 3D structures with gate-all-around configuration. The ferroelectric material layer is positioned between the gate electrode and channel region in a vertical stacking arrangement, enabling higher integration density by utilizing the third dimension (vertical direction) rather than continuing to scale lateral dimensions alone.
Solution Approach 2:
The patent employs a composite structure integrating ferroelectric material layer with standard semiconductor materials (silicon channel, metal gates, dielectric layers). This composite approach combines the non-volatile memory properties of ferroelectric materials with the成熟的 manufacturing processes of CMOS technology, achieving high density while maintaining manufacturability at nanometer nodes.
2Reliability
If logic circuits and non-volatile memory circuits are incorporated within one chip to achieve higher performance, then device performance improves, but device complexity increases
Solution Approach 1:
The vertical gate-all-around ferroelectric memory structure uses a universal fabrication process flow that is compatible with standard CMOS logic circuit manufacturing. The same deposition, etching, and patterning tools and techniques used for logic devices can be applied to form the memory structures, enabling co-integration of logic and non-volatile memory on the same chip without requiring separate specialized process lines.
Solution Approach 2:
The patent segments the memory cell structure into distinct functional layers (channel region, ferroelectric material layer, gate electrode, source/drain regions) that can be independently optimized and manufactured. This modular segmentation allows for systematic integration with logic circuits while maintaining clear process control and reducing overall device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances device density and performance by leveraging the hysteresis effect of ferroelectric materials for data storage, providing fast write/read speeds, low power consumption, and cost-effectiveness in manufacturing.
Implementation Method 1
leveraging the hysteresis effect of ferroelectric materials for data storage
Data Source
AI summary
Various embodiments of the present disclosure provide a semiconductor device structure. The semiconductor device structure includes a device layer having a first side and a second side opposing the first side, and a first interconnect structure disposed over the first side of the device layer. The first interconnect structure includes a first interconnect-level layer, a second interconnect-level layer disposed over the first interconnect-level layer, wherein the second interconnect-level layer comprises an array of vertical-type memory cell devices. The semiconductor device structure also includes a third interconnect-level layer disposed over the second interconnect-level layer.