Vertical GAA FET SRAM Cell Layout for Area Reduction
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Solution Overview
Problem
The semiconductor industry faces challenges in developing SRAM devices with higher density, performance, lower power consumption, and lower costs, particularly in designing and fabricating three-dimensional structures like Fin FETs and vertical FETs, where effective control of channel layers and suppression of short channel effects are crucial.
Innovation Solution
The introduction of new layout structures and configurations for SRAM using vertical GAA (gate all around) FET devices with nano-scale channel layers, allowing for more uniform layout and improved control over channel surfaces, which reduces power consumption and enhances design flexibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If conventional planar FET structures are used in SRAM, then fabrication is simpler, but device density and area efficiency are limited
Solution Approach 1:
The patent transitions from conventional planar FET structures to vertical FET structures, utilizing the vertical dimension to achieve higher device density. The vertical channel extends perpendicular to the substrate surface, allowing multiple devices to be stacked in the vertical direction rather than only occupying horizontal plane space, thereby reducing the area required per SRAM cell while managing the increased structural complexity through systematic vertical integration.
2Area of moving object
If vertical FET structures are adopted to reduce area, then device density increases, but control of channel layers becomes more difficult
Solution Approach 1:
The patent implements gate-all-around (GAA) structures where multiple gate electrodes are nested around the vertical channel in a concentric arrangement. This nested configuration provides comprehensive electrostatic control of the channel from all directions (top, bottom, and sidewalls), ensuring precise control of carrier flow despite the vertical orientation. The nested gate structure effectively manages channel layer control in the vertical FET by surrounding the channel with control electrodes.
Solution Approach 2:
The patent employs composite material structures including semiconductor-sacrificial layer combinations for channel formation, high-k dielectric materials for gate insulation, and metal silicide contacts. These composite material systems enable precise control of vertical channel properties while maintaining manufacturability. The carefully selected material combinations provide the necessary electrical, mechanical, and thermal properties to control the vertical channel layer effectively.
3Length of moving object
If channel length is reduced to increase density, then device size decreases, but short channel effects increase
Solution Approach 1:
The gate-all-around structure with multiple nested gate electrodes provides enhanced electrostatic control over the short vertical channel. The concentric arrangement of gates surrounding the channel from all directions creates strong electric field control that suppresses short channel effects even when the channel length is reduced to increase device density. This nested gate configuration effectively extends the control range into the deep sub-micron regime.
Solution Approach 2:
By transitioning to vertical channel orientation with gate-all-around control, the patent achieves effective short channel effect suppression in the vertical dimension while maintaining reduced horizontal footprint. The vertical channel geometry combined with multi-directional gate control creates superior electrostatic management compared to planar structures, enabling scaled channel lengths without sacrificing reliability.
Data Source
AI summary
An SRAM includes an SRAM array including a plurality of SRAM cells arranged in a matrix. Each of the SRAM cells includes six vertical field effect transistors. The SRAM array includes a plurality of groups of conductive regions extending in the column direction. Each of the plurality of groups of conductive regions includes a first to a fourth conductive region arranged in this order in the row direction, and the first to fourth conductive regions are separated by insulating regions from each other. The first, second and third conductive regions are coupled to sources of first conductive type VFETs, and the fourth conductive region is coupled to sources of second conductive type VFETs. The plurality of groups are arranged in the row direction such that the fourth conductive region of one group of conductive regions is adjacent to the first conductive region of adjacent one group of conductive regions.