Vertical GAA Memory Structure for Higher Density Without Linewidth Shrink
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge in integrated circuit manufacturing is to reduce device linewidth and increase storage density in memory devices, as the integration degree and storage capacity are limited by the size of the memory device, particularly with the transition from embedded word line structures to gate-all-around (GAA) structures.
Innovation Solution
A semiconductor structure is designed with a base, bit lines, active structures, and memory structures where the word line surrounds the channel regions of the active layers, allowing for a thin active layer that reduces linewidth and enables three-dimensional stacking of transistors and capacitors, enhancing storage density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the device linewidth is reduced to increase storage density, then the storage density increases, but the manufacturing precision and device reliability deteriorate
Solution Approach 1:
The patent transitions from planar device architecture to three-dimensional vertical stacking, where multiple active layers are stacked perpendicular to the substrate. This dimensional change allows storage density to increase vertically rather than requiring further linewidth reduction in the lateral plane, thereby avoiding the manufacturing precision challenges associated with sub-10nm lithography.
Solution Approach 2:
The device is segmented into multiple discrete active layers (first active layer, second active layer, etc.) stacked vertically, with each layer containing source-drain regions, channel regions, and support regions. This segmentation allows independent formation and optimization of each layer, improving manufacturability while achieving high density through vertical integration.
2Device complexity
If the device linewidth is reduced to improve integration degree, then the integration degree increases, but the operating speed and power consumption characteristics deteriorate
Solution Approach 1:
By stacking multiple active layers vertically, the patent achieves high integration degree without further reducing the lateral dimensions of individual devices. This preserves the electrical performance characteristics of each device while increasing the number of devices per unit area through vertical stacking, thereby maintaining operating speed.
Solution Approach 2:
Multiple active layers are nested vertically within the same lateral footprint, with each layer containing complete transistor structures. This nesting approach allows high integration while maintaining adequate device dimensions for optimal electrical performance, avoiding the speed degradation associated with excessive linewidth reduction.
3Length of moving object
If the GAA structure is adopted to reduce linewidth, then the linewidth reduction is achieved, but the device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent adopts a vertical stacking architecture where multiple active layers are arranged perpendicular to the substrate, replacing the need for extreme linewidth reduction. This dimensional change simplifies the lateral structure while achieving high density through vertical integration, reducing manufacturing complexity compared to continuing to scale lateral dimensions.
Solution Approach 2:
The complex three-dimensional structure is segmented into multiple two-dimensional active layers that can be formed using standard planar processing techniques followed by vertical stacking. Each layer contains simplified source-drain, channel, and support regions that are easier to manufacture than attempting to create equivalent functionality through lateral scaling alone.
Data Source
AI summary
Embodiments of the present disclosure relate to the field of semiconductors, and provide a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a base and a bit line that extends along a first direction; active structures, wherein the active structure includes at least two active layers arranged at intervals, the active layer includes a first source-drain region, a channel region, a second source-drain region, and a support region, and the bit line is connected to the first source-drain region; a word line extending along a second direction, wherein the word line is connected to an adjacent active structure, and the word line surrounds at least two channel regions included in the connected active structure; and a memory structure perpendicularly stacked on the base, where the memory structure is connected to the second source-drain region, and the memory structure surrounds the support region.