Vertical Complementary GAA MOSFET Structure for Short-Channel Control
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Solution Overview
Problem
Existing semiconductor technologies face challenges in achieving full depletion in channel regions and minimizing short-channel effects in FinFETs and gate-all-around FETs, particularly at sub-10-15 nm technology nodes, due to the lack of gate control over the bottom part of the channel.
Innovation Solution
The development of complementary MOSFETs with vertically stacked gate-all-around transistors, where a first GAA FET is disposed over a substrate and a second GAA FET is positioned above, with a common gate structure surrounding the channel region, and the source/drain regions are electrically separated, allowing for improved gate control and reduced short-channel effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If FinFET gate structure is used to reduce device area, then area is reduced, but gate control over channel is insufficient leading to short-channel effects
Solution Approach 1:
The patent transitions from planar 2D gate control to 3D gate-all-around control by wrapping the gate electrode around the channel region in three dimensions. This dimensional change allows the gate to control the channel from all directions (top, bottom, and sides), achieving full depletion and eliminating short-channel effects while maintaining compact device area.
2Productivity
If transistor dimensions are scaled down to sub 10-15 nm nodes to increase device density, then device density is improved, but short-channel effects increase due to reduced gate control
Solution Approach 1:
At sub-10-15 nm nodes, the patent employs gate-all-around FET structures where the gate electrode completely surrounds the channel region in three dimensions. This 3D configuration provides strong electrostatic control over the scaled-down channel, achieving full depletion and suppressing short-channel effects even as device dimensions are reduced to increase density.
Solution Approach 2:
The gate electrode is nested around the channel region, with the gate dielectric layer interposed between them. This nested configuration allows the gate to control the channel from all directions, providing enhanced electrostatic control that compensates for the reduced channel dimensions at sub-10-15 nm nodes.
3Reliability
If vertically stacked GAA FETs are implemented to improve gate control, then gate control is enhanced, but device complexity increases
Solution Approach 1:
The patent combines multiple FETs into vertically stacked configurations where n-type and p-type GAA FETs are integrated along the vertical axis. This merging approach achieves full depletion and superior gate control while maintaining compact footprints, though it does increase fabrication process complexity.
Solution Approach 2:
By stacking FETs vertically in the third dimension rather than arranging them laterally, the patent achieves enhanced gate control and full depletion. This vertical integration improves space utilization and gate control effectiveness, though it requires complex alignment and fabrication processes.
Data Source
AI summary
A fin including a bottom portion, a first sacrificial layer disposed over the bottom portion, a first semiconductor layer disposed over the first sacrificial layer, a second sacrificial layer disposed over the first semiconductor layer and a second semiconductor layer disposed over the second sacrificial layer, is formed. The second semiconductor layer protrudes from a first insulating layer. A dummy gate is formed over the second semiconductor layer. A sidewall spacer layer is formed on side faces of the dummy gate. A first dielectric layer is formed over the dummy gate and the sidewall spacer layer. The dummy gate is removed, thereby forming a gate space. The first insulating layer is etched in the gate space, thereby exposing the first semiconductor layer and the first and second sacrificial layers. The first and second sacrificial layers are removed. A gate dielectric layer and a gate electrode layer are formed.