Vertical Gate-All-Around Structure With Precise Spacer and Gate Length
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Solution Overview
Problem
Vertical GAA devices face challenges such as short channel effect, gate-to-contact time-dependent dielectric breakdown, and parasitic contact resistance due to difficulties in controlling spacer thickness and gate length precision as IC device sizes shrink.
Innovation Solution
The use of silicon/silicon germanium channel epi deposition and subsequent silicon germanium recess and spacer deposition processes to control top and bottom spacer thicknesses and gate length with greater precision, improving the performance and yield of vertical GAA devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fabrication processes are used for vertical GAA devices, then device complexity is reduced, but manufacturing precision of spacer thickness and gate length deteriorates
Solution Approach 1:
The fabrication process is divided into distinct stages: forming semiconductor layers with different materials (Si/SiGe), selective removal of specific layers, and sequential deposition of spacers. This segmentation allows precise control of spacer thickness and gate length through independent process steps, directly resolving the manufacturing precision issue while managing complexity through structured organization.
Solution Approach 2:
Different regions of the device receive different treatments: SiGe layers are selectively removed in certain areas while Si layers are retained, and spacers are deposited only in specific locations. This local differentiation enables precise control of gate length and spacer dimensions in critical areas without affecting the entire device structure, thereby improving manufacturing precision.
2Productivity
If IC device sizes are scaled down, then functional density is improved, but manufacturing precision of spacer thickness and gate length deteriorates
Solution Approach 1:
The invention changes the material parameter by using SiGe semiconductor layers with different etch selectivity compared to Si layers. This parameter change enables selective removal of SiGe while retaining Si, providing precise control over gate length and spacer dimensions even as overall device sizes scale down to increase functional density.
Solution Approach 2:
SiGe layers serve as intermediary sacrificial structures that facilitate precise dimensioning. These intermediary layers are deposited, patterned, and selectively removed to define the final gate and spacer dimensions, acting as a mediator that enables precise control at scaled dimensions without directly forming the final functional structures.
3Reliability
If spacer thickness and gate length control is improved, then device performance is improved, but fabrication process complexity increases
Solution Approach 1:
SiGe sacrificial layers are deposited and patterned in advance before the final gate and spacer formation. This preliminary action establishes precise dimensional templates that guide subsequent processing steps, ensuring device performance through pre-defined spacer thickness and gate length while organizing complexity into manageable sequential stages.
Solution Approach 2:
The invention exploits parameter changes in material properties (etch selectivity between Si and SiGe) to achieve precise dimensional control. By changing the material parameter and utilizing selective removal, the process achieves high device performance through controlled spacer and gate dimensions while managing fabrication complexity through material-based differentiation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the precision and uniformity of spacer thicknesses and gate lengths, thereby improving the performance and yield of vertical GAA devices by reducing undesirable size variations and optimizing device characteristics.
Implementation Method 1
silicon/silicon germanium channel epi deposition
Implementation Method 2
silicon germanium recess
Data Source
AI summary
A vertically protruding structure is formed. The vertically protruding structure includes a substrate, a first semiconductor layer disposed over the substrate, a channel layer disposed over the first semiconductor layer, and a second semiconductor layer disposed over the channel layer. The first semiconductor layer and the second semiconductor layer each contain a first type of semiconductive material. The channel layer contains a second type of semiconductive material different from the first type. First recesses are formed in the first semiconductor layer and the second semiconductor layer. Each of the first recesses protrudes laterally inward. The first recesses are filled with dielectric spacers. The channel layer and the substrate are laterally trimmed. The remaining portions of the channel layer and the dielectric spacers define second recesses that protrude laterally inward. Gate structures are formed in the second recesses.