Vertical GAA Memory Cell With Stacked Capacitor for Higher Density
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Solution Overview
Problem
Existing 1T1C memory devices, with planar transistors and capacitors, occupy significant space, limiting device density and integration in integrated circuits.
Innovation Solution
A vertical gate-all-around (GAA) transistor with a vertically stacked capacitor structure, where the capacitor is directly contacted by the source or drain of the transistor, reducing passive device area and increasing density by integrating the memory device on the frontside or backside of a semiconductor structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If planar transistors and capacitors are used in 1T1C memory devices, then the device structure is simple and easy to manufacture, but the device occupies significant space limiting device density
Solution Approach 1:
The patent transitions from planar 2D device layout to vertical 3D stacked architecture. The memory device comprises a transistor vertically stacked with a capacitor, where the capacitor is positioned directly above the transistor body. This vertical stacking enables three-dimensional utilization of space, dramatically reducing the horizontal footprint of each memory cell while maintaining electrical functionality.
2Productivity
If device dimensions are reduced to improve production efficiency and lower costs, then production efficiency improves and costs decrease, but the complexity of IC manufacturing processes increases
Solution Approach 1:
The memory device is segmented into distinct functional blocks: a transistor portion and a capacitor portion vertically stacked together. Each portion can be formed through separate processing steps using existing manufacturing technologies, allowing the complex 3D structure to be built incrementally from simpler components using established fabrication processes.
Solution Approach 2:
The capacitor structure is nested above the transistor body, with the capacitor portion containing electrodes and dielectric layers that are vertically integrated over the transistor. This nested arrangement allows multiple functional elements to occupy overlapping vertical spaces, maximizing space utilization without requiring proportionally more manufacturing complexity.
3Quantity of substance
If more devices are integrated into a smaller area to increase device density, then device density improves, but the existing planar structure cannot further decrease in size
Solution Approach 1:
The invention exploits the vertical dimension by stacking the capacitor directly above the transistor, transforming the device architecture from planar to three-dimensional. This vertical integration allows multiple memory cells to be packed more densely in the horizontal plane, as each cell occupies minimal footprint while utilizing vertical space for its components.
Data Source
AI summary
One aspect of the present disclosure pertains to a memory device. The memory device includes a semiconductor feature made of a compound semiconductor material. The semiconductor features includes a first portion as a first source/drain (S/D) feature, a second portion as a channel, and a third portion as a second S/D feature. The first portion is above the second portion and the second portion is above the third portion, and the second portion vertically extends from the first portion to the third portion. The memory device includes a gate structure horizontally wrapping around the second portion and a capacitor structure in direct contact with and wrapping around the semiconductor feature.