Vertical GAA Semiconductor Stack With Step Structures for Higher Density
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Solution Overview
Problem
Planar semiconductor devices face limitations in scaling down due to their parallel source, gate, and drain arrangement, making it difficult to increase integration density, whereas vertical devices with perpendicular arrangements can be more easily scaled and stacked for higher integration.
Innovation Solution
A semiconductor apparatus with vertically stacked devices of different widths, where the source/drain and gate components protrude to form step and sub-step structures, allowing for electrical connection and increased integration density by forming a Gate-All-Around (GAA) configuration through sacrificial gates and epitaxial growth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If planar device arrangement is used, then manufacturing process is simple, but integration density cannot be increased further due to scaling limitations
Solution Approach 1:
The patent transitions from planar (2D) device arrangement to vertical (3D) stacking configuration. Multiple semiconductor devices are stacked vertically with different widths, creating a three-dimensional structure that increases integration density while maintaining manufacturing feasibility through sequential layer formation processes
2Quantity of substance
If vertical devices are stacked to increase integration density, then integration density is improved, but device structure becomes more complex requiring step structures for electrical connection
Solution Approach 1:
The patent segments the vertical stack into multiple devices with different widths. Each device is formed in a separate layer with controlled horizontal dimensions, creating distinct segments that can be independently configured. This segmentation allows electrical connections to be made at different vertical levels through step structures, managing complexity through modular layer design
Solution Approach 2:
The patent implements a nested structure where narrower devices are positioned above wider devices in the vertical stack. The step structures create nested horizontal profiles, with each upper device nested within the horizontal footprint of lower devices. This nesting approach enables electrical connections while maintaining compact vertical integration
3Power
If devices with different widths are vertically stacked, then driving current and channel width variation are improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies local quality by creating devices with different horizontal dimensions at different vertical positions in the stack. Each device layer is patterned with specific width characteristics suited to its function, with lower devices having larger widths for higher current handling and upper devices having smaller widths. This local differentiation achieves varied driving current capabilities while using standard semiconductor fabrication techniques
Data Source
AI summary
Disclosed are a semiconductor apparatus, a manufacturing method, and an electronic device. The semiconductor apparatus includes first and second devices vertically stacked. Each of the first and second devices includes a first source/drain layer, a channel layer and a second source/drain layer vertically stacked, and a gate stack surrounding a periphery of the channel layer. The first device protrudes in a first direction relative to the second device to form a first step. A second step is defined by the second device. On a side in a second direction intersecting with the first direction, the first source/drain layer of each device protrudes in the second direction relative to the second source/drain layer and gate stack, to form a sub-step. Each sub-step is on a corresponding step. On another side in the second direction, the gate stack of each device protrudes in the second direction relative to the second source/drain layer.