Vertical GAA Gate Structure for Threshold Voltage Stabilization
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Solution Overview
Problem
Advanced semiconductor technology faces challenges in maintaining consistent threshold voltage in vertical FETs, particularly when using indium gallium zinc oxide (IGZO) as a channel material, leading to variations that can result in product yield issues due to annealing processes.
Innovation Solution
The implementation of a vertical gate-all-around (GAA) structure with multiple gate electrodes, including an inner and outer gate, allows for independent biasing to adjust the threshold voltage, thereby stabilizing it and improving yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a vertical FET structure with IGZO channel material is used, then device density and current density are improved, but threshold voltage variation increases leading to yield issues
Solution Approach 1:
The gate structure is segmented into multiple independent gate electrodes (first gate electrode, second gate electrode, third gate electrode) that can be biased separately. This segmentation allows independent control of threshold voltage in different regions of the vertical FET, enabling compensation for voltage variations and improving overall threshold voltage consistency while maintaining high device density.
Solution Approach 2:
The patent implements dynamic threshold voltage control through separate biasing of multiple gate electrodes. By applying different voltages to each gate electrode, the threshold voltage can be dynamically adjusted and optimized during device operation, thereby maintaining consistency despite process variations in IGZO channel material.
2Manufacturing precision
If annealing processes are applied to IGZO channel material, then material quality is improved, but threshold voltage variation increases
Solution Approach 1:
The patent applies preliminary anti-action by using multiple gate electrodes with separate biasing capability to counteract the threshold voltage variations induced by annealing processes. The independent gates can be configured to compensate for the specific variations introduced during annealing, thereby maintaining threshold voltage consistency despite the beneficial material quality improvements from annealing.
3Reliability
If multiple gate electrodes are implemented, then threshold voltage control is improved, but device complexity increases
Solution Approach 1:
The gate electrodes are arranged in a nested configuration where the second gate electrode is positioned between the first and third gate electrodes along the vertical channel. This nested arrangement allows multiple gates to be integrated in a compact vertical structure, improving threshold voltage control while minimizing the increase in device footprint and overall complexity.
Solution Approach 2:
The patent transitions from a planar gate structure to a vertical three-dimensional gate arrangement. The multiple gate electrodes are stacked vertically along the channel length, utilizing the vertical dimension to provide independent control points. This dimensional change enables enhanced threshold voltage stability without significantly increasing lateral device complexity.
Data Source
AI summary
The present disclosure provides a semiconductor structure. The semiconductor structure includes: a first doped structure over a substrate and a second doped structure over the first doped structure and the substrate; a first gate layer, at last partially disposed between the first doped structure and the second doped structure; a first gate dielectric layer, surrounding the first gate layer; a channel layer, surrounding the first gate dielectric layer; a second gate dielectric layer, surrounding the channel layer; and a second gate layer, surrounding the second gate dielectric layer. A manufacturing method for forming the same is also provided.