Vertical GAA Transistor Structure for Low Off-State Current
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Solution Overview
Problem
Miniaturized transistors with vertical channel configurations face challenges in accurately forming back gate electrodes and experience increased area occupation, leading to higher off-state currents and power consumption due to short-channel effects.
Innovation Solution
A semiconductor device structure with a first and second gate electrode configuration, where the second gate electrode is positioned to surround the semiconductor layer, forming a gate-all-around (GAA) structure, and using insulating layers to manage oxygen supply and reduce oxygen vacancies, enabling accurate formation and reduced area occupation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If a vertical channel configuration is used to miniaturize transistors, then area occupation is reduced and on-state current is improved, but manufacturing precision for back gate electrode formation deteriorates and off-state current increases due to short-channel effects
Solution Approach 1:
The patent transitions from planar gate electrode configuration to a three-dimensional gate-all-around structure where the gate electrode wraps around the semiconductor channel in multiple dimensions. This dimensional change enables precise positioning of the gate electrode relative to the channel while maintaining miniaturization, as the gate controls the channel from all directions rather than just from above or below.
Solution Approach 2:
The gate electrode is positioned to surround the semiconductor layer, creating a nested configuration where the gate encloses the channel region. This nesting approach allows the gate to be in close proximity to the channel from multiple angles, improving control precision without increasing the overall transistor footprint area.
2Area of moving object
If a vertical channel configuration is used to miniaturize transistors, then area occupation is reduced, but off-state current increases due to short-channel effects
Solution Approach 1:
By implementing a gate-all-around structure in three dimensions, the patent enhances the electric field control over the channel from all directions. This multi-dimensional gating suppresses short-channel effects more effectively than planar configurations, reducing off-state current while maintaining the compact vertical channel design.
Solution Approach 2:
The insulating layers are positioned to supply oxygen to the semiconductor layer before the transistor operates, preventing oxygen vacancies that would otherwise increase off-state current. This preliminary oxygen supply prepares the semiconductor material in advance to maintain low leakage characteristics during vertical channel operation.
3Reliability
If insulating layers are used to manage oxygen supply, then oxygen vacancies are reduced and reliability is improved, but device complexity increases
Solution Approach 1:
The insulating layers serve multiple functions simultaneously: they provide electrical insulation between conductive elements, supply oxygen to prevent oxygen vacancies in the semiconductor layer, and structurally support the gate-all-around configuration. This multi-functionality reduces the need for separate dedicated oxygen supply structures, thereby limiting the increase in device complexity.
Data Source
AI summary
A semiconductor device includes first to fourth conductive layers, first and second insulating layers, and a semiconductor layer. The first insulating layer is over the first conductive layer. The second conductive layer is over the first insulating layer. The second conductive layer and the first insulating layer include an opening reaching the first conductive layer. The semiconductor layer is in the opening. The second insulating layer is over the semiconductor layer. The third conductive layer is over the second insulating layer to fill the opening. The first insulating layer includes a depressed portion surrounding the opening in a plan view. The fourth conductive layer fills the depressed portion. Inside the opening, one side of the semiconductor layer faces the third conductive layer with the second insulating layer therebetween, and the other side of the semiconductor layer faces the fourth conductive layer with the first insulating layer therebetween.