Self-Aligned Word Line Formation in Vertical GAA Transistors
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge in semiconductor manufacturing is the difficulty in forming precise word lines and controlling doping concentrations in high-density semiconductor structures, particularly for vertical gate-all-around transistors, which affects electrical performance and integration density due to limitations in etching precision and equipment capabilities.
Innovation Solution
A method is introduced that involves forming semiconductor channels with a first and second doped region, using different dielectric layers to create gaps for self-aligned word line formation without etching, and an insulating layer to protect doped regions, allowing for accurate and small-sized word line creation, and forming junctionless transistors to simplify the process and improve integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional etching methods are used to form word lines, then the manufacturing process follows traditional steps, but the etching precision is insufficient and word line size control is difficult
Solution Approach 1:
The patent applies preliminary action by pre-forming the word line pattern using a mandrel structure before the actual word line deposition. The mandrel is formed with the desired final word line dimensions, and subsequent self-aligned processes transfer this pattern without requiring high-precision etching. This resolves the contradiction by achieving precise word line formation through preliminary patterning rather than relying on difficult etching steps.
Solution Approach 2:
The patent introduces a mandrel as an intermediary structure that mediates the word line formation process. The mandrel serves as a template that defines the word line pattern, allowing indirect formation of word lines with high precision. This intermediary approach avoids the need for direct high-precision etching while maintaining control over word line dimensions.
2Area of stationary object
If vertical gate-all-around transistors are used to reduce area, then integration density improves, but word line etching becomes difficult within some size ranges
Solution Approach 1:
The patent uses preliminary action by forming the word line pattern through self-aligned deposition on pre-formed mandrels rather than through etching. This approach enables precise word line formation in small-size vertical GAA transistors where conventional etching becomes difficult, thus resolving the contradiction between small transistor area and precise word line formation.
Solution Approach 2:
The patent replaces the mechanical etching process with a deposition-based self-aligned formation process. Instead of using etching to define word lines, the method uses conformal deposition on mandrels followed by planarization, substituting a more controllable process that works better at small dimensions required for high-density vertical GAA transistors.
3Reliability
If doping concentration control is required in high-density structures, then electrical performance can be optimized, but the process complexity increases
Solution Approach 1:
The patent applies preliminary action by performing doping operations at specific stages before final structure formation. The doping is performed on pre-defined regions using the self-aligned mandrel structure, which simplifies the doping process by eliminating the need for complex masking and alignment steps. This achieves both good electrical performance through controlled doping and reduced process complexity.
Solution Approach 2:
The patent employs self-service through self-aligned processes where the mandrel structure automatically defines the doping regions and word line positions. The same mandrel that defines the word line pattern also serves as the mask for doping operations, eliminating the need for separate masking processes and reducing overall process complexity while maintaining precise doping control.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
The present disclosure provides a semiconductor structure and a manufacturing method thereof. The manufacturing method includes: providing a base; forming bit lines on the base, and forming semiconductor channels on surfaces of the bit lines away from the base, the semiconductor channel including a first doped region, a channel region and a second doped region arranged sequentially; forming a first dielectric layer, the first dielectric layer surrounding sidewalls of the semiconductor channels, and a first gap being provided between parts of the first dielectric layer located on sidewalls of adjacent semiconductor channels on a same bit line; forming a second dielectric layer, the second dielectric layer filling up the first gaps, and a material of the second dielectric layer being different from a material of the first dielectric layer; removing a part of the first dielectric layer to expose sidewalls of the channel regions; forming an insulating layer, covering at least sidewall surfaces of the channel regions, and second gaps being provided between the insulating layer and the second dielectric layer; and forming word lines, the word lines filling up the second gaps.