Vertical GaN FET Fabrication on CTE-Matched Engineered Substrates
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Solution Overview
Problem
Gallium nitride (GaN) based Field Effect Transistor (FET) devices grown epitaxially on sapphire substrates face issues such as decreased uniformity and performance reliability due to mismatched coefficients of thermal expansion (CTE), leading to performance and reliability concerns.
Innovation Solution
A method for fabricating vertical FET integrated circuits using an engineered substrate with a polycrystalline ceramic core, a barrier layer, and a substantially single crystalline layer, where the CTE matches that of the epitaxial gallium nitride layers, enabling the formation of trenches, gates, sources, and a drain layer, along with an interconnect structure and metal bonding layer, to enhance epitaxial growth and device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If GaN-based FET devices are grown epitaxially on sapphire substrates, then the devices can be manufactured using conventional heteroepitaxial growth processes, but the mismatched coefficients of thermal expansion result in decreased uniformity and performance reliability
Solution Approach 1:
The patent introduces an intermediate substrate layer between the sapphire substrate and the GaN epitaxial layers. This intermediate layer acts as a mediator that is lattice-matched to both the sapphire substrate and the GaN layers, thereby reducing the thermal expansion mismatch and improving device reliability while maintaining compatibility with conventional heteroepitaxial growth processes
Solution Approach 2:
The patent employs a composite substrate structure consisting of multiple layers with different material properties. The composite structure combines sapphire substrate with intermediate buffer layers and potentially other functional layers, creating a graded transition that mitigates the thermal expansion mismatch and improves overall device performance and reliability
2Ease of manufacture
If heteroepitaxial growth is used on mismatched substrates, then the manufacturing process can be simplified, but the uniformity of the epitaxial layers deteriorates
Solution Approach 1:
The intermediate substrate layer serves as a mediator that provides a lattice-matched interface between the sapphire substrate and GaN epitaxial layers, enabling uniform growth without complicating the overall manufacturing process
Solution Approach 2:
The patent modifies the substrate structure by introducing intermediate layers with specific lattice parameters that are matched to both the sapphire substrate and GaN layers, thereby improving epitaxial layer uniformity while maintaining process simplicity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the creation of high-power vertical FETs with improved current flow and reduced leakage current, suitable for high-power operation and applicable to FinFETs and trench MOSFETs, while maintaining low gate voltage operation.
Implementation Method 1
using an engineered substrate and a plurality of groups of epitaxial layers, where the coefficient of thermal expansion (CTE) of the engineered substrate substantially matches the CTE of the epitaxial layers
Data Source
AI summary
A method of fabricating a semiconductor device includes providing an engineered substrate. The method further includes forming an epitaxial gallium nitride (GaN) layer coupled to the engineered substrate, forming a plurality of trenches in the epitaxial GaN layer, and forming a plurality of gates in the trenches. The method further includes forming a plurality of sources coupled to the epitaxial GaN layer, forming an interconnect structure on the gates and sources, forming a metal bonding layer on the interconnect structure, bonding a conductive carrier to the metal bonding layer, removing the engineered substrate, forming a drain layer on the back surface of the epitaxial GaN layer, etching at least one portion of the epitaxial GaN layer and the interconnect structure to form at least one gate pad recess and expose the embedded metal track; and forming at least one gate electrode in the gate pad recess.