3D Vertical GaN Transistors With Sidewall Heterojunction Control
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Solution Overview
Problem
Conventional power electronic devices with lateral GaN transistors face issues such as current slump, increased size, manufacturing complexity, and lower performance due to surface traps and the need for field plates to mitigate surface breakdown, leading to higher costs and complexity.
Innovation Solution
The development of vertical transistors with three-dimensional structures made of wide bandgap semiconductor materials, such as GaN, which include a substrate, an array of 3D structures, a sidewall heterojunction layer, and an isolation region, allowing for independent tuning of turn-on and breakdown voltages by adjusting the geometry of the 3D structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If lateral GaN transistors are used to achieve wide bandgap semiconductor device functionality, then the device can handle higher breakdown voltages and temperatures, but the device size increases and surface traps cause current slump and lower performance
Solution Approach 1:
The patent transitions from conventional lateral (2D) transistor architecture to a vertical (3D) transistor architecture. This dimensional change allows the current flow to proceed vertically through the device structure rather than laterally across the surface, thereby eliminating the harmful effects of surface traps that cause current slump in lateral devices while maintaining the wide bandgap material advantages for high voltage and temperature operation
2Temperature
If lateral GaN transistors are used to achieve wide bandgap semiconductor device functionality, then the device can handle higher breakdown voltages and temperatures, but the device size increases leading to higher cost and manufacturing complexity
Solution Approach 1:
By adopting a vertical transistor architecture, the patent achieves high voltage and temperature capability within a smaller footprint compared to lateral devices. The vertical current flow path allows for more efficient use of the device area, reducing the overall device size and associated manufacturing complexity and cost while maintaining the desired high-temperature and high-breakdown-voltage performance
Solution Approach 2:
The patent employs independent tuning of turn-on and breakdown voltages through geometric parameters of the vertical structure. By adjusting dimensions such as the height and cross-sectional area of the vertical channel, the device characteristics can be optimized without increasing overall device size, thereby reducing manufacturing complexity while achieving the required voltage and temperature performance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances device performance by increasing speed and power while reducing costs through smaller die sizes, improving reliability and efficiency by minimizing surface traps and manufacturing complexity.
Implementation Method 1
a sidewall heterojunction layer positioned on at least one vertical sidewall of each 3D structure. The sidewall heterojunction layer includes a second semiconductor material, where the first and second semiconductor material have different bandgaps.
Data Source
AI summary
An apparatus includes at least one vertical transistor, where the at least one vertical transistor includes: a substrate including a first semiconductor material, an array of three dimensional (3D) structures above the substrate, a sidewall heterojunction layer positioned on at least one vertical sidewall of each 3D structure, and an isolation region positioned between the 3D structures. Each 3D structure includes the first semiconductor material. The sidewall heterojunction layer includes a second semiconductor material, where the first and second semiconductor material have different bandgaps.