Vertical GaN JFET with Segmented Gate for Low Capacitance
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Solution Overview
Problem
Conventional power electronics face challenges in minimizing gate-to-drain capacitance, which affects switching speeds and voltage management in vertical junction gate field-effect transistors (JFETs), particularly due to high defect densities and limitations in growing GaN layers on foreign substrates.
Innovation Solution
The use of gallium-nitride (GaN) epitaxial layers on pseudo-bulk GaN substrates to fabricate vertical JFETs with reduced gate-to-drain capacitance, employing edge termination structures and III-nitride semiconductor materials to optimize conductivity and breakdown voltage, while minimizing the Miller effect through strategic doping and layer thickness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional vertical JFET structures are used, then manufacturing is simpler, but gate-to-drain capacitance is high which reduces switching speed
Solution Approach 1:
The gate structure is segmented into a gate region and a source-coupled region that are spatially separated by a gap. This segmentation reduces the overlapping area between gate and drain, thereby reducing gate-to-drain capacitance and improving switching speed while maintaining manufacturability through defined separation zones.
Solution Approach 2:
The patent introduces a vertical dimension to the gate structure by extending the gate into a vertical channel region. This vertical configuration allows the gate to be positioned above the channel rather than alongside it, reducing lateral overlap with the drain and decreasing gate-to-drain capacitance while enabling faster switching.
2Speed
If gate-to-drain capacitance is reduced, then switching speed improves, but voltage division between gate-to-source and gate-to-drain capacitance becomes problematic
Solution Approach 1:
The patent creates different local qualities in the gate structure by forming a heavily doped source-coupled region adjacent to the source and a lightly doped gate region above the channel. This local differentiation ensures that the gate-to-source capacitance remains dominant while the gate-to-drain capacitance is minimized, achieving both fast switching and proper voltage division.
Solution Approach 2:
The patent changes the doping parameters of the gate structure, creating a heavily doped source-coupled region (1E19 to 1E21 atoms/cm³) and a lightly doped gate region (1E16 to 1E18 atoms/cm³). This parameter variation optimizes the capacitance distribution to ensure gate-to-source capacitance dominates, enabling reliable voltage management during switching.
3Ease of manufacture
If GaN layers are grown on foreign substrates, then manufacturing is easier, but defect density increases reducing device reliability
Solution Approach 1:
The patent uses a buffer layer as an intermediary between the foreign substrate (silicon or sapphire) and the GaN channel layer. This buffer layer mediates the lattice mismatch and thermal expansion differences, reducing defect density and improving device reliability while maintaining the manufacturing advantage of using readily available foreign substrates.
Data Source
AI summary
An embodiment of a vertical power device includes a III-nitride substrate, a drift region coupled to the III-nitride substrate and comprising a III-nitride material of a first conductivity type, and a channel region coupled to the drift region and comprising a III-nitride material of the first conductivity type. The vertical power device also includes a source region coupled to the channel region and comprising a III-nitride material of the first conductivity type, and a gate region coupled to the channel region. The gate region includes a III-nitride material of a second conductivity type. The vertical power device further includes a source-coupled region coupled to the drift region and electrically connected with the source region. The source-coupled region includes a III-nitride material of the second conductivity type.