Vertical GaN Chip Package With Leadframe Thermal Pathways
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Solution Overview
Problem
Existing GaN chip packaging technologies face challenges in achieving low package resistance, high thermal efficiency, and reduced electromagnetic interference while maintaining cost-effectiveness and miniaturization, particularly due to limitations in laminate-based solutions and solder material constraints.
Innovation Solution
A chip package design featuring a stack of plate-shaped metal carrier structures and GaN chips arranged vertically relative to the application board, with alternating face-up and face-down orientations, utilizing leadframe technology to connect chip pads and carrier structures, and embedded in a mold compound for enhanced electrical and thermal performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If laminate-based package solutions are used for GaN chips, then footprint design flexibility is improved, but package cost increases and solder material options are limited
Solution Approach 1:
The patent employs leadframe technology instead of expensive laminate substrates, using cost-effective metal carrier structures that can be mass-produced through conventional leadframe manufacturing processes, thereby reducing package cost while maintaining design flexibility
Solution Approach 2:
The patent uses composite metal carrier structures with redistribution layers that combine different materials (metal carriers, conductive redistribution layers, insulating layers) to achieve both cost-effectiveness and design flexibility in the package structure
2Adaptability or versatility
If laminate-based package solutions are used for GaN chips, then footprint design flexibility is improved, but package resistance increases
Solution Approach 1:
The patent implements localized high-quality conductive paths through thick metal redistribution layers in the leadframe structure, concentrating low-resistance pathways at critical bonding interfaces while maintaining design flexibility in non-critical areas
Solution Approach 2:
The patent uses composite metal carrier structures with redistribution layers that combine different materials (metal carriers, conductive redistribution layers, insulating layers) to achieve both cost-effectiveness and design flexibility in the package structure
3Area of stationary object
If miniaturization is pursued in GaN chip packaging, then footprint area is reduced, but thermal dissipation capability may be compromised
Solution Approach 1:
The patent transitions from planar two-dimensional packaging to three-dimensional vertical stacking, arranging multiple GaN chips and metal carriers in alternating layers along the vertical axis, thereby reducing footprint area while maintaining thermal dissipation through vertical heat pathways
Solution Approach 2:
The patent merges multiple functional layers (GaN chips, metal carriers, redistribution layers) into a compact vertical stack where electrical and thermal pathways are integrated, achieving miniaturization without compromising thermal management
4Adaptability or versatility
If vertical stacking of multiple GaN chips is implemented, then device functionality is enhanced, but package complexity increases
Solution Approach 1:
The patent divides the package into repeating modular units of GaN chips sandwiched between metal carriers, with each unit performing specific electrical and thermal functions, allowing scalable complexity while maintaining manufacturing simplicity through repetition of standardized building blocks
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The vertical arrangement and leadframe technology facilitate low package resistance, improved thermal dissipation, reduced electromagnetic interference, and cost-effective miniaturization, enhancing overall device performance and reliability.
Implementation Method 1
utilizing leadframe technology to connect chip pads and carrier structures, and embedded in a mold compound for enhanced electrical and thermal performance
Implementation Method 2
The vertical arrangement and leadframe technology facilitate low package resistance, improved thermal dissipation
Data Source
Figure 1A~2
Figure 3A~4B
Figure 5A~5D
AI summary
A chip package includes a first plate-shaped metal carrier structure, a second plate-shaped metal carrier structure and a third plate-shaped metal carrier structure. The chip package further includes a first GaN chip sandwiched between the first metal carrier structure and the second metal carrier structure and a second GaN chip sandwiched between the second metal carrier structure and the third metal carrier structure. The chip package is configured to be attached to an application board in an orientation in which the plate-shaped metal carrier structures and the GaN chips are inclined, in particular vertical relative to the application board.